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The SST36VF1601C and SST36VF1602C are 1M x16 or 2M x8 CMOS Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS Super- Flash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The devices write (Program or Erase) with a 2.7-3.6V power supply and conform to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Program, these devices provide a typical Program time of 7 sec and use the Toggle Bit, Data# Polling, or RY/BY# to detect the completion of the Program or Erase operation. To protect against inadvertent write, the devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the devices significantly improve performance and reliability, while lowering power consumption. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
• Organized as 1M x16 or 2M x8 • Dual Bank Architecture 16 Mbit Bottom Sector Protection - SST36VF1601C: 12 Mbit + 4 Mbit 16 Mbit Top Sector Protection - SST36VF1602C: 4 Mbit + 12 Mbit • Single 2.7-3.6V for Read and Write Operations • Superior Reliability Endurance: 100,000 cycles (typical) Greater than 100 years Data Retention • Low Power Consumption: Active Current: 6 mA typical Standby Current: 4 A typical Auto Low Power Mode: 4 A typical • Hardware Sector Protection/WP# Input Pin Protects the 4 outermost sectors (8 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high • Hardware Reset Pin (RST#) Resets the internal state machine to reading array data • Byte# Pin Selects 8-bit or 16-bit mode • Sector-Erase Capability Uniform 2 KWord sectors • Chip-Erase Capability • Block-Erase Capability Uniform 32 KWord blocks • Erase-Suspend / Erase-Resume Capabilities • Security ID Feature SST: 128 bits User: 128 bits • Fast Read Access Time 70 ns • Latched Address and Data • Fast Erase and Program (typical): Sector-Erase Time: 18 ms Block-Erase Time: 18 ms Chip-Erase Time: 35 ms Program Time: 7 s • Automatic Write Timing Internal VPP Generation • End-of-Write Detection Toggle Bit Data# Polling Ready/Busy# pin • CMOS I/O Compatibility • Conforms to Common Flash Memory Interface (CFI) • JEDEC Standards Flash EEPROM Pinouts and command sets • Packages Available 48-ball TFBGA (6mm x 8mm) 48-lead TSOP (12mm x 20mm) Non-Pb (lead-free) packages available • All non-Pb (lead-free) devices are RoHS compliant