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SST32HF6482C, SST32HF64A1, SST32HF64A1-70-4E-LFS

Table of contents:
Info of SST32HF6482C
Info of SST32HF64A1
Info of SST32HF64A1-70-4E-LFS

SST32HF6482C, SST32HF64A1, SST32HF64A1-70-4E-LFS Selling Leads, Datasheet

MFG:SST Package Cooled:06+ D/C:M530023+

SST32HF6482C, SST32HF64A1, SST32HF64A1-70-4E-LFS Picture

SST32HF6482C, SST32HF64A1, SST32HF64A1-70-4E-LFS Datasheet download

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Part Number: SST32HF6482C

MFG: SST

Package Cooled: 06+

D/C: M530023+

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SST32HF64A1 General Description

The SST32HF64Ax/64Bx ComboMemory devices integrate a CMOS flash memory bank with a CMOS PseudoSRAM (PSRAM) memory bank in a Multi-Chip Package (MCP), manufactured with SST's proprietary, high-performance SuperFlash technology. Featuring high-performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 sec. To protect against inadvertent flash write, the SST32HF64x/64Bx devices contain on-chip hardware and software data protection schemes. The SST32HF64Ax/64Bx devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST32HF64Ax/64Bx devices consist of two independent memory banks with respective bank enable signals. The flash and PSRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#.

The memory bank selection is done by memory bank enable signals. The PSRAM bank enable signal, BES1# selects the PSRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.

The SST32HF64Ax/64Bx provide the added functionality of being able to simultaneously read from or write to the PSRAM bank while erasing or programming in the flash memory bank. The PSRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the PSRAM bank can be accessed for Read or Write.

SST32HF64A1 Maximum Ratings

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V_DD¹+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . -1.0V to V_DD¹+1.0V
Package Power Dissipation Capability (T_A = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. V_DD = V_DDF and V_DDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.

SST32HF64A1 Features

• ComboMemories organized as:
SST32HF64Ax: 4M x16 Flash + 1024K x16 PSRAM
SST32HF64Bx: 4M x16 Flash + 2048K x16 PSRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
Read from or Write to PSRAM while Erase/Program Flash
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
Active Current: 15 mA (typical) for Flash or PSRAM Read
Standby Current: 60 A (typical)
• Flexible Erase Capability
Uniform 2 KWord sectors
Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
SST: 128 bits; User: 128 bits
• Fast Read Access Times:
Flash: 70 ns
PSRAM: 70 ns
• Hardware Block-Protection/WP# Input Pin
Bottom Block-Protection (bottom 32 KWord) for SST32HF64x1
Top Block-Protection (top 32 KWord) for SST32HF64x2
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 s (typical)
• Flash Automatic Erase and Program Timing
Internal VPP Generation
• Flash End-of-Write Detection
Toggle Bit
Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
64-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant

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