SST32HF1641C, SST32HF1642, SST32HF1642C Selling Leads, Datasheet
MFG:SST Package Cooled:06+
SST32HF1641C, SST32HF1642, SST32HF1642C Datasheet download
Part Number: SST32HF1641C
MFG: SST
Package Cooled: 06+
D/C:
SST32HF1641C, SST32HF1642, SST32HF1642C
- Table of contents:
Info of SST32HF1641C
Info of SST32HF1642
Info of SST32HF1642C
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About SST32HF1641C
PDF/DataSheet Download
Datasheet: SST32HF1641C
File Size: 441623 KB
Manufacturer: SST
Download : Click here to Download
About SST32HF1642
PDF/DataSheet Download
Datasheet: SST32HF1642
File Size: 441623 KB
Manufacturer: SST
Download : Click here to Download
About SST32HF1642C
PDF/DataSheet Download
Datasheet: SST32HF1642C
File Size: 441623 KB
Manufacturer: SST
Download : Click here to Download
SST32HF1641C General Description
The SST32HFx1/x1C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST's proprietary, high performance SuperFlash technology. The SST32HF16x1/32x1 devices use a PseudoSRAM. The SST32HF16x1C/32x1C devices use standard SRAM.
Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 sec. To protect against inadvertent flash write, the SST32HFx1/x1C devices contain on-chip hardware and software data protection schemes. The SST32HFx1/x1C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.
The SST32HFx1/x1C devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.
The SST32HFx1/x1C provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write.
SST32HF1641C Maximum Ratings
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0W
Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C for 10 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
1. VDD = VDDF and VDDS
2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0W
Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C for 10 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
1. VDD = VDDF and VDDS
2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
SST32HF1641C Features
• ComboMemories organized as:
SST32HF1621C: 1M x16 Flash + 128K x16 SRAM
SST32HF1641x: 1M x16 Flash + 256K x16 SRAM
SST32HF1681: 1M x16 Flash + 256K x16 SRAM
SST32HF3241x: 2M x16 Flash + 256K x16 SRAM
SST32HF3281: 2M x16 Flash + 512K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
Read from or Write to SRAM while Erase/Program Flash
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
Active Current: 15 mA (typical) for Flash or SRAM Read
Standby Current:
- SST32HFx1: 60 A (typical)
- SST32HFx1C: 12 A (typical)
• Flexible Erase Capability
Uniform 2 KWord sectors
Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
SST: 128 bits; User: 128 bits
• Hardware Block-Protection/WP# Input Pin
Bottom Block-Protection (bottom 32 KWord)
• Fast Read Access Times:
Flash: 70 ns
SRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 s (typical)
• Flash Automatic Erase and Program Timing
Internal VPP Generation
• Flash End-of-Write Detection
Toggle Bit
Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
63-ball LFBGA (8mm x 10mm x 1.4mm)
62-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
SST32HF1621C: 1M x16 Flash + 128K x16 SRAM
SST32HF1641x: 1M x16 Flash + 256K x16 SRAM
SST32HF1681: 1M x16 Flash + 256K x16 SRAM
SST32HF3241x: 2M x16 Flash + 256K x16 SRAM
SST32HF3281: 2M x16 Flash + 512K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
Read from or Write to SRAM while Erase/Program Flash
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
Active Current: 15 mA (typical) for Flash or SRAM Read
Standby Current:
- SST32HFx1: 60 A (typical)
- SST32HFx1C: 12 A (typical)
• Flexible Erase Capability
Uniform 2 KWord sectors
Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
SST: 128 bits; User: 128 bits
• Hardware Block-Protection/WP# Input Pin
Bottom Block-Protection (bottom 32 KWord)
• Fast Read Access Times:
Flash: 70 ns
SRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 s (typical)
• Flash Automatic Erase and Program Timing
Internal VPP Generation
• Flash End-of-Write Detection
Toggle Bit
Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
63-ball LFBGA (8mm x 10mm x 1.4mm)
62-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
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