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SST310T-T1, SST31LF021, SST31LF021-70-4C

Table of contents:
Info of SST310T-T1
Info of SST31LF021
Info of SST31LF021-70-4C

SST310T-T1, SST31LF021, SST31LF021-70-4C Selling Leads, Datasheet

MFG:SIL Package Cooled:06+ D/C:0440+

SST310T-T1, SST31LF021, SST31LF021-70-4C Picture

SST310T-T1, SST31LF021, SST31LF021-70-4C Datasheet download

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Part Number: SST310T-T1

MFG: SIL

Package Cooled: 06+

D/C: 0440+

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SST31LF021 General Description

The SST31LF021/021E devices are a 256K x8 CMOS flash memory bank combined with a 128K x8 or 32K x8 CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. Two pinout standards are available for these devices. The SST31LF021 conform to JEDEC standard flash pinouts and the SST31LF021E conforms to standard EPROM pinouts.

The SST31LF021/021E devices write (SRAM or flash) with a 3.0-3.6V power supply. The monolithic SST31LF021/021E devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. Featuring high performance Byte-Program, the flash memory bank provides a maximum Byte-Program time of 20 µsec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 4 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF021/ 021E devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF021/ 021E devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST31LF021/021E operate as two independent memory banks with respective bank enable signals. The SRAM and flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LF021/021E provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector- Erase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write.

The SST31LF021/021E devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LF021/021E devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LF021/021E inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

The SST31LF021/021E devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LF021/021E devices are offered in 32-lead TSOP packages. See Figure 1 for the pinouts.

SST31LF021 Maximum Ratings

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . .. -1.0V to V_DD+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.

SST31LF021 Features

• Monolithic Flash + SRAM ComboMemory
   SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM
• Single 3.0-3.6V Read and Write Operations
• Concurrent Operation
   Read from or Write to SRAM while Erase/Program Flash
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
   Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read
Standby Current: 10 µA (typical)
• Flash Sector-Erase Capability
   Uniform 4 KByte sectors
• Latched Address and Data for Flash
• Fast Read Access Times:
   SST31LF021 Flash: 70 ns SRAM: 70 ns
   SST31LF021E Flash: 300 ns SRAM: 300 ns
• Flash Fast Erase and Byte-Program:
   Sector-Erase Time: 18 ms (typical)
   Bank-Erase Time: 70 ms (typical)
   Byte-Program Time: 14 µs (typical)
   Bank Rewrite Time: 4 seconds (typical)
• Flash Automatic Erase and Program Timing
   Internal VPP Generation
• Flash End-of-Write Detection
   Toggle Bit
   Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
   32-lead TSOP (8mm x 14mm)

SST31LF021 Connection Diagram

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