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SN65LVDT33PWR, SN65LVDT33PWRG4, SN65LVDT34

Table of contents:
Info of SN65LVDT33PWR
Info of SN65LVDT33PWRG4
Info of SN65LVDT34

SN65LVDT33PWR, SN65LVDT33PWRG4, SN65LVDT34 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:n/a D/C:09+

SN65LVDT33PWR, SN65LVDT33PWRG4, SN65LVDT34 Datasheet download

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Part Number: SN65LVDT33PWR

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: n/a

D/C: 09+

Description: IC DIFF RECEIVER H-S 16-TSSOP

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SN65LVDT33PWR Parameters

Technical/Catalog Information	SN65LVDT33PWR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	0/4
Type	Receiver
Voltage - Supply	3 V ~ 3.6 V
Package / Case	16-TSSOP
Packaging	Tape & Reel (TR)
Protocol	RS644
Drawing Number	296; 4040064; PW; 8, 14, 16, 20, 24, 28
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN65LVDT33PWR SN65LVDT33PWR

SN65LVDT33PWRG4 Parameters

Technical/Catalog Information	SN65LVDT33PWRG4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	0/4
Type	Receiver
Voltage - Supply	3 V ~ 3.6 V
Package / Case	16-TSSOP
Packaging	Tape & Reel (TR)
Protocol	RS644
Drawing Number	296; 4040064; PW; 8, 14, 16, 20, 24, 28
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN65LVDT33PWRG4 SN65LVDT33PWRG4

SN65LVDT34 General Description

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

SN65LVDT34 Maximum Ratings

Supply voltage range, V_CC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . .−0.5 V to 4 V
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. .. . . . .−1 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . .−5 V to 6 V
 V_A − V_B (LVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . .. . . . . . . . . . . . . .1 V
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . .. .Class 3, A: 15 kV, B: 500 V
Charged-device mode: All pins (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±500 V
Continuous power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C

SN65LVDT34 Typical Application

A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the limitations seen in present solutions. A detailed theory of operation is presented in application note The Active Failsafe Feature of the SN65LVDS32B, literature number SLLA082A.

The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.

SN65LVDT34 Connection Diagram

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