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SN65LVDS104PWG4, SN65LVDS104PWRG4, SN65LVDS105

Table of contents:
Info of SN65LVDS104PWG4
Info of SN65LVDS104PWRG4
Info of SN65LVDS105

SN65LVDS104PWG4, SN65LVDS104PWRG4, SN65LVDS105 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:n/a D/C:09+

SN65LVDS104PWG4, SN65LVDS104PWRG4, SN65LVDS105 Datasheet download

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Part Number: SN65LVDS104PWG4

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: n/a

D/C: 09+

Description: IC 1:4 LVDS CLOCK BUFFER 16TSSOP

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SN65LVDS104PWG4 Parameters

Technical/Catalog Information	SN65LVDS104PWG4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	4/1
Type	Clock Buffer
Voltage - Supply	3 V ~ 3.6 V
Package / Case	16-TSSOP
Packaging	Tube
Protocol	LVDS
Drawing Number	296; 4040064; PW; 8, 14, 16, 20, 24, 28
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN65LVDS104PWG4 SN65LVDS104PWG4

SN65LVDS104PWRG4 Parameters

Technical/Catalog Information	SN65LVDS104PWRG4
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Number of Drivers/Receivers	4/1
Type	Clock Buffer
Voltage - Supply	3 V ~ 3.6 V
Package / Case	16-TSSOP
Packaging	Tape & Reel (TR)
Protocol	LVDS
Drawing Number	296; 4040064; PW; 8, 14, 16, 20, 24, 28
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	SN65LVDS104PWRG4 SN65LVDS104PWRG4

SN65LVDS105 General Description

The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, lownoise coupling, and switching speeds to transmit data at speeds up to 655 Mbps at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 W. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

The SN65LVDS104 and SN65LVDS105 are characterized for operation from 40°C to 85°C.

SN65LVDS105 Maximum Ratings

Supply voltage range, V_CC(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 4 V
Voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .0.5 to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 4 V
Electrostatic discharge (see Note 2); Y, Z, and GND . . . . . . . . . . . . . . . . . . . .Class 3, A:16 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . .. . . . . .260°C

SN65LVDS105 Typical Application

A LVDS receiver can be used to receive various other types of logic signals. Figure 19 through Figure 28 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.

SN65LVDS105 Connection Diagram

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