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The SN65LV1023 serializer and SN65LV1224 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 30 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 360-Mbps and 792-Mbps payload encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023 and SN65LV1224 are characterized for operation over ambient air temperature of 40°C to 85°C.
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN65LV1023 Features
· 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock · Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224 · Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz · Synchronization Mode for Faster Lock · Lock Indicator · No External Components Required for PLL · Low-Cost 28-Pin SSOP Package · Industrial Temperature Qualified, TA = −40°C to 85°C · Programmable Edge Trigger on Clock · Flow-Through Pinout for Easy PCB Layout