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PC744, PC7447, PC7447A

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PC744, PC7447, PC7447A Selling Leads, Datasheet

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PC744, PC7447, PC7447A Datasheet download

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PC7447 Parameters

PC7447 Datasheet and Application Notes

PC7457-RISC Microprocessor Preliminary

PC7447 General Description

This document is primarily concerned with the PowerPC™ PC7457; however, unless otherwise noted, all information here also applies to the PC7447. The PC7457 and PC7447 are implementations of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the PC7457.

The PC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The PC7457 consists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high-bandwidth interface. The PC7447 is identical to the PC7457 except it does not support the L3 cache interface.

The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes may be used as cache; the remaining 2M bytes must be private memory. Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455 application if the core power supply is 1.3V.

PC7447 Maximum Ratings

Symbol	Characteristic		Maximum Value	Unit
V_DD⁽²⁾	Core supply voltage		-0.3 to 1.60	V
AV_DD⁽²⁾	PLL supply voltage		-0.3 to 1.60	V
OV_DD⁽³⁾⁽⁴⁾	Processor bus supply voltage	BVSEL = 0	-0.3 to 1.95	V
OV_DD⁽³⁾⁽⁵⁾	Processor bus supply voltage	BVSEL = HRESET or OV_DD	-0.3 to 2.7	V
GV_DD⁽³⁾⁽⁶⁾	L3 bus supply voltage	L3VSEL = ¬HRESET	-0.3 to 1.65	V
GV_DD⁽³⁾⁽⁷⁾		L3VSEL = 0	-0.3 to 1.95	V
GV_DD⁽³⁾⁽⁸⁾		L3VSEL = HRESET or GV_DD	-0.3 to 2.7	V
V_IN^(9)(10)	Input voltage	Processor bus	-0.3 to OV_DD+ 0.3	V
V_IN^(9)(10)		L3 bus	-0.3 to GV_DD + 0.3	V
V_IN		JTAG signals	-0.3 to OV_DD + 0.3	V
T_STG	Storage temperature range		-55 to 150	°C

Notes:
1. Functional and tested operating conditions are given in Table 3 on page 12. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. BVSEL must be set to 0, such that the bus is in 1.8V mode.
5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6. L3VSEL must be set to ¬HRESET (inverse of HRESET ), such that the bus is in 1.5V mode.

PC7447 Typical Application

PC7457-RISC Microprocessor Preliminary

PC7447A General Description

The PC7447A host processor is a high-performance, low-power, 32-bit implementa-tions of the PowerPC Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Motorola®'s AltiVec™ technology.

This microprocessor is ideal for leading-edge embedded computing and signal pro-cessing applications. The PC7447A features 512 KB of on-chip L2 cache. The PC7447A microprocessor has no backside L3 cache, allowing for a smaller package designed as a pin-for-pin replacement for the PC7447 microprocessor. This device benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to help deliver tremendous power savings without sacrificing speed. A low-power version of the PC7447A microprocessor is also available.

Figure 1 shows a block diagram of the PC7447A. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multi-media unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to the main memory and other system resources.

Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447 application if the core power supply is 1.3V.

PC7447A Maximum Ratings

Symbol	Characteristic		MaximumValue	Unit
V_DD(2) A_VDD(2) O_VDD(3)(4) O_VDD(3)(5) V_IN(6)(7) V_INT_STG	Core supply voltage PLL supply voltage Processor bus supply voltage Input voltage Storage temperature range	BVSEL = 0 BVSEL = HRESET or OV_DDProcessor bus JTAG signals	-0.3 to 1.60 -0.3 to 1.60 -0.3 to 1.95 -0.3 to 2.7 -0.3 to OV_DD + 0.3 -0.3 to OV_DD + 0.3 -55 to 150	V V V V V V °C

Notes:1.Functional and tested operating conditions are given in Table 3 on page 10. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2.Caution: V_DD/A_VDD must not exceed O_VDD by more than 1V during normal operation; this limit may be exceeded for a maxi-mum of 20 ms during the power-on reset and power-down sequences.
3.Caution: O_VDD must not exceed V_DD/A_VDD by more than 2V during normal operation; this limit may be exceeded for a maxi-mum of 20 ms during the power-on reset and power-down sequences.
4.BVSEL must be set to 0, such that the bus is in 1.8V mode.
5.BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6.Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset.
7.VIN may overshoot/undershoot to a voltage and for a maximum duration shown in Figure 3 on page 10.

PC7447A Features

•3000 Dhrystone 2.1 MIPS at 1.3 GHz
•Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
•Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
•P_D Typically 18W at 1.33 GHz at V_DD = 1.3V; 8.0W at 1 GHz at V_DD = 1.1V Full Operating Conditions
•Nap, Doze and Sleep Power Saving Modes
•Superscalar (Four Instructions Fetched Per Clock Cycle)
•4 GB Direct Addressing Range
•Virtual Memory: 4 Hexabytes (2⁵²)
•64-bit Data and 36-bit Address Bus Interface
•Integrated L1: 32 KB Instruction and 32 KB Data Cache
•Integrated L2: 512 KB
•11 Independent Execution Units and 3 Register Files
•Write-back and Write-through Operations
•f_INTMax = 1.33 GHz (1.42 GHz to be Confirmed)
•f_BUS Max = 133 MHz/166 MHz

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