MN39571PT, MN39571PTL, MN395929L1-A Selling Leads, Datasheet
MFG:PAN Package Cooled:DIP D/C:05+
MN39571PT, MN39571PTL, MN395929L1-A Datasheet download
Part Number: MN39571PT
MFG: PAN
Package Cooled: DIP
D/C: 05+
MFG:PAN Package Cooled:DIP D/C:05+
MN39571PT, MN39571PTL, MN395929L1-A Datasheet download
MFG: PAN
Package Cooled: DIP
D/C: 05+
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
TOP
PDF/DataSheet Download
Datasheet: MN39571PT
File Size: 48447 KB
Manufacturer: PANASONIC [Panasonic Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MN3000
File Size: 165865 KB
Manufacturer: PANASONIC [Panasonic Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MN3000
File Size: 165865 KB
Manufacturer: PANASONIC [Panasonic Semiconductor]
Download : Click here to Download
Parameter |
Symbol |
Rating |
Operating condition |
Unit | ||||
min |
max |
min |
typ |
max | ||||
Output drain voltage |
VOD |
- 0.2 |
18.0 |
15.2 |
15.5 |
15.8 |
V | |
Reset drain voltage |
VRD |
- 0.2 |
18.0 |
15.2 |
15.5 |
15.8 |
V | |
Input source voltage |
VIS |
- 0.2 |
18.0 |
15.2 |
15.5 |
15.8 |
V | |
Protection P-well voltage |
VPT *2 |
- 10.0 |
0.2 |
- 9.3 |
- 9.0 |
- 8.7 |
V | |
P-well voltage |
VPW |
Reference voltage |
- |
0 |
- |
V | ||
Output load transistor gate voltage |
VLG |
- |
- |
Supplied internally |
V | |||
Output gate voltage |
VOG |
- |
- |
Supplied internally |
V | |||
Reset` pulse voltage |
H-L |
VRG(H-L) *3 |
- |
8.0 |
3.0 |
3.3 |
3.6 |
V |
Bias |
VRG(Bias)*3 |
- 0.5 |
- |
Supplied internally |
V | |||
Horizontal register clock pulse voltage 1 |
VH1(H) |
- |
8.0 |
3.0 |
3.3 |
3.6 |
V | |
VH1(L) |
-0.2 |
- |
-0.2 |
0 |
0.2 |
V | ||
Horizontal register clock pulse voltage 2 |
VH2(H) |
- |
8.0 |
3.0 |
3.3 |
3.6 |
V | |
VH2(L) |
-0.2 |
- |
-0.2 |
0 |
0.2 |
V | ||
Vertical shift register clock pulse voltage 1,5 |
VV1,5(H)*2 |
- |
18.0 |
15.2 |
15.5 |
15.8 |
V | |
VV3,7(M)*2 |
- |
- |
-0.2 |
0 |
0.2 |
V | ||
VV3,7(L)*2 |
- 10.0 |
- |
- 9.3 |
- 9.0 |
- 8.7 |
V | ||
Vertical shift register clock pulse voltage 3,7 |
VV1,5(H)*2 |
- |
18.0 |
15.2 |
15.5 |
15.8 |
||
VV2,6(M)*2 |
- |
15.0 |
-0.2 |
0 |
0.2 |
V | ||
VV2,6(L)*2 |
- 10.0 |
- 9.3 |
- 9.0 |
- 8.7 |
V | |||
Vertical shift register clock pulse voltage 2,6 |
VV4,8(M)*2 |
- |
15.0 |
-0.2 |
0 |
0.2 |
V | |
VV4,8(L)*2 |
- 10.0 |
- 9.3 |
- 9.0 |
- 8.7 |
V | |||
Vertical shift register clock pulse voltage 4,8 |
VV4,8(M)*2 |
- |
15.0 |
-0.2 |
0 |
0.2 |
V | |
VV4,8(L)*2 |
- 10.0 |
- |
- 9.3 |
- 9.0 |
- 8.7 |
V | ||
Substrate voltage |
VSub*2 |
Supplied internally |
V | |||||
VSub*4,*5 |
- 0.2 |
45.0 |
26.5 |
27.0 |
27.5 |
V | ||
Operating temperature |
Topr |
- 10 |
60 |
- |
25 |
- |
°C | |
Storage temperature |
Tstg |
- 30 |
70 |
- |
- |
- |
°C |
Note)
1. Standard light input defines
Standard light input is the one when the exposure is done at a lens aperture of F8, using a light source of 2856 K and 1050 nt, and placing a color temperature conversion filter LB-40 (HOYA) and an IR cutting filter CAW-500 (t = 2.5 mm) in the light path.
2. *1: VSub internal settings guarantee blooming at 400 times light input of the standard light input.
3. *2: VPT is set so that the following conditions are set for VL of the vertical shift clock. VPT VL
supply is recommended for fVSub
· Photographic grade super high resolution by 2,310k pixels in type-1/2 format
· Responds to 5:1 skipping readout mode for LCD monitoring
· The same aspect ratio of 3:2 as a 35mm film
· Newly developed small plastic package Outline dimensions : 14.0mm(W) × 12.4mm(D) × 3.4mm(t)(Without lead pins)