MD1-200TA, MD1208AAJ-5-120, MD1210 Selling Leads, Datasheet
MFG:BIT Package Cooled:Module D/C:N/A
MD1-200TA, MD1208AAJ-5-120, MD1210 Datasheet download
Part Number: MD1-200TA
MFG: BIT
Package Cooled: Module
D/C: N/A
MFG:BIT Package Cooled:Module D/C:N/A
MD1-200TA, MD1208AAJ-5-120, MD1210 Datasheet download
MFG: BIT
Package Cooled: Module
D/C: N/A
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PDF/DataSheet Download
Datasheet: MD1001
File Size: 179777 KB
Manufacturer: Centronic
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MD1001
File Size: 179777 KB
Manufacturer: Centronic
Download : Click here to Download
PDF/DataSheet Download
Datasheet: MD1210
File Size: 182952 KB
Manufacturer: SUTEX [Supertex, Inc]
Download : Click here to Download
The Supertex MD1210 is a high speed, dual MOSFET driver. It is designed to drive high voltage N- and P-channel MOSFET transistors for medical ultrasound applications and other application requiring a high output current for a capacitive load. The high-speed input stage of the MD1210 can operate from 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation.
The output stage of the MD1210 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5.0 and 5.0 volts, and the output L and H levels may be varied anywhere over the range of 5.0 to +5.0 volts. The output stage is capable of peak currents of up to ±2.0 amps, depending on the supply voltages used and load capacitance present.
The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A output high and the B output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.
VDD-VSS, Logic Supply Voltage |
-0.5V to +13.5V |
VH, Output High Supply Voltage |
VL-0.5V to VDD+0.5V |
VL, Output Low Supply Voltage |
VSS-0.5V to VH+0.5V |
VSS, Low Side Supply Voltage |
-7.0V to +0.5V |
Logic Input Levels |
VSS-0.5V to VSS+7.0V |
Maximum Junction Temperature |
+125°C |
Storage Temperature |
-65°C to 150°C |
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.