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MC9S12DJ512, MC9S12DJ512CPV, MC9S12DJ512CPVE

Table of contents:
Info of MC9S12DJ512
Info of MC9S12DJ512CPV
Info of MC9S12DJ512CPVE

MC9S12DJ512, MC9S12DJ512CPV, MC9S12DJ512CPVE Selling Leads, Datasheet

MFG:FREESCALE Package Cooled:QFP D/C:2009

MC9S12DJ512, MC9S12DJ512CPV, MC9S12DJ512CPVE Picture

MC9S12DJ512, MC9S12DJ512CPV, MC9S12DJ512CPVE Datasheet download

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Part Number: MC9S12DJ512

MFG: FREESCALE

Package Cooled: QFP

D/C: 2009

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MC9S12DJ512 General Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block Guides of the individual IP blocks on the device.

MC9S12DJ512 Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V_SS5 or V_DD5).

Num	Rating	Symbol	Min	Max	Unit
1	I/O, Regulator and Analog Supply Voltage	V_DD5	-0.3	6.0	V
2	Digital Logic Supply Voltage ²	V_DD	-0.3	3.0	V
3	PLL Supply Voltage ²	V_DDPLL	-0.3	3.0	V
4	Voltage difference VDDX to VDDR and VDDA	D_VDDX	-0.3	0.3	V
5	Voltage difference VSSX to VSSR and VSSA	D_VSSX	-0.3	0.3	V
6	Digital I/O Input Voltage	V_IN	-0.3	6.0	V
7	Analog Reference	V_RH, V_RL	-0.3	6.0	V
8	XFC, EXTAL, XTAL inputs	V_ILV	-0.3	3.0	V
9	TEST input	V_TEST	-0.3	10.0	V
10	Instantaneous Maximum Current Single pin limit for all digital I/O pins ³	I_D	-25	+25	mA
11	Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL⁴	I_DL	-25	+25	mA
12	Instantaneous Maximum Current Single pin limit for TEST ⁵	I_DT	-0.25	0	mA
13	Storage Temperature Range	T_stg	65	155

MC9S12DJ512 Features

• HCS12 Core
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer's model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Module Mapping Control)
INT (Interrupt control)
BKP (Breakpoints)
BDM (Background Debug Mode)
• CRG (Clock and Reset Generation)
Low current Colpitts oscillator or
Pierce oscillator
PLL
COP watchdog
Real Time Interrupt
Clock Monitor
• 8-bit and 4-bit ports with interrupt functionality
Digital filtering
Programmable rising or falling edge trigger
• Memory
512K Flash EEPROM
4K byte EEPROM
14K byte RAM
• Two 8-channel Analog-to-Digital Converters
10-bit resolution
External conversion trigger capability
• Five 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
• Enhanced Capture Timer
16-bit main counter with 7-bit prescaler
8 programmable input capture or output compare channels
Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
Programmable period and duty cycle
8-bit 8-channel or 16-bit 4-channel
Separate control for each pulse width and duty cycle
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Fast emergency shutdown input
Usable as interrupt inputs
• Serial interfaces
Two asynchronous Serial Communications Interfaces (SCI)
Three Synchronous Serial Peripheral Interface (SPI)
• Byte Data Link Controller (BDLC)
SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
• Inter-IC Bus (IIC)
Compatible with I²C Bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP package
I/O lines with 5V input and drive capability
5V A/D converter inputs
Operation at 50MHz equivalent to 25MHz Bus Speed over -40 <= TA <= 125
Development support
Single-wire background debug™ mode (BDM)
On-chip hardware breakpoints

MC9S12DJ512 Connection Diagram

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