M312L5128AU1, M312L5128AU1-CCC, M312L5128MT0 Selling Leads, Datasheet
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M312L5128AU1, M312L5128AU1-CCC, M312L5128MT0 Datasheet download
Part Number: M312L5128AU1
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D/C: 09+
M312L5128AU1, M312L5128AU1-CCC, M312L5128MT0
- Table of contents:
Info of M312L5128AU1
Info of M312L5128AU1-CCC
Info of M312L5128MT0
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About M310X
PDF/DataSheet Download
Datasheet: M310X
File Size: 373551 KB
Manufacturer:
Download : Click here to Download
About M310X
PDF/DataSheet Download
Datasheet: M310X
File Size: 373551 KB
Manufacturer:
Download : Click here to Download
About M312L5128MT0
PDF/DataSheet Download
Datasheet: M312L5128MT0
File Size: 182479 KB
Manufacturer: SAMSUNG [Samsung semiconductor]
Download : Click here to Download
M312L5128MT0 Maximum Ratings
|
Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to Vss |
VIN, VOUT |
-0.5 ~ 3.6 |
V |
| Voltage on VDD supply relative to Vss |
VDD,VDDQ |
-1.0 ~ 3.6 |
V |
| Storage temperature |
TSTG |
-55 ~ +150 |
A/ch |
| Power dissipation |
PD |
1.5 * # of component |
|
| Short circuit current |
IOS |
50 |
mA |
Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
M312L5128MT0 Features
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Serial presence detect with EEPROM
• 1,200mil height & double sided
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Serial presence detect with EEPROM
• 1,200mil height & double sided
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