IDT72245L50J, IDT72245L815PF, IDT72245LB Selling Leads, Datasheet
MFG:IDT Package Cooled:PLCC D/C:93+
IDT72245L50J, IDT72245L815PF, IDT72245LB Datasheet download
Part Number: IDT72245L50J
MFG: IDT
Package Cooled: PLCC
D/C: 93+
MFG:IDT Package Cooled:PLCC D/C:93+
IDT72245L50J, IDT72245L815PF, IDT72245LB Datasheet download
MFG: IDT
Package Cooled: PLCC
D/C: 93+
Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.
TOP
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT 79R3081
File Size: 914564 KB
Manufacturer: IDT
Download : Click here to Download
PDF/DataSheet Download
Datasheet: IDT72245LB
File Size: 186166 KB
Manufacturer: IDT
Download : Click here to Download
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOsare applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output.
The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain technique. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FL is grounded on the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated using IDT's high-speed submicron CMOS technology.
Symbol |
Rating |
Com'l & Ind'l |
Unit |
VTERM |
Terminal Voltage with respect to GND |
0.5 to +7.0 |
V |
TSTG |
Storage Temperature |
55 to +125 |
°C |
IOUT |
DC Output Current |
50 to +50 |
°C |