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DSP56321, DSP56321FC220, DSP56321FC240

Table of contents:
Info of DSP56321
Info of DSP56321FC220
Info of DSP56321FC240

DSP56321, DSP56321FC220, DSP56321FC240 Selling Leads, Datasheet

MFG:MOTOROLA Package Cooled:BGA D/C:07+

DSP56321, DSP56321FC220, DSP56321FC240 Picture

DSP56321, DSP56321FC220, DSP56321FC240 Datasheet download

Five Points

Part Number: DSP56321

MFG: MOTOROLA

Package Cooled: BGA

D/C: 07+

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DSP56321 Maximum Ratings

Rating¹	Symbol	Value^{1, 2}	Unit
Supply Voltage³	V_CC	0.1 to 2.25	V
Input/Output Supply Voltage³	V_CCQH	0.3 to 4.35	V
All input voltages	V_IN	GND 0.3 to V_CCQH + 0.3	V
Current drain per pin excluding V_CC and GND	I	10	mA
Operating temperature range	T_J	40 to +100	°C
Storage temperature	T_STG	55 to +150	°C

Notes: 1. GND = 0 V, V_CC = 1.6 V ± 0.1 V, V_CCQH = 3.3 V ± 0.3 V, T_J = 40°C to +100°C, CL = 50 pF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
3. Power-up sequence: During power-up, and throughout the DSP56321 operation, V_CCQH voltage must always be higher or equal to V_CC voltage.

DSP56321 Features

• 200 million multiply-accumulates per second (MMACS) (400 MMACS using the EFCOP in filtering applications) with a 200 MHz clock at 1.6 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action Group (JTAG) Test Access Port (TAP)

DSP56321 Typical Application

• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• Security encryption systems
• Home entertainment systems
• DSP resource boards
• High-speed modem banks
• IP telephony

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