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CY7C428-55PC, CY7C4285-ASC, CY7C4285V

Table of contents:
Info of CY7C428-55PC
Info of CY7C4285-ASC
Info of CY7C4285V

CY7C428-55PC, CY7C4285-ASC, CY7C4285V Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:PDIP28 D/C:93+/98+

CY7C428-55PC, CY7C4285-ASC, CY7C4285V Picture

CY7C428-55PC, CY7C4285-ASC, CY7C4285V Datasheet download

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Part Number: CY7C428-55PC

MFG: CYPRESS

Package Cooled: PDIP28

D/C: 93+/98+

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CY7C4285V General Description

The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN).

When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4255/65/75/85V have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices.

Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO andRXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to V_SS and theFL pin of all the remaining devices should be tied to V_CC.

CY7C4285V Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ 65°C to +150°C
Ambient Temperature with
Power Applied............................................ 55°C to +125°C
Supply Voltage to Ground Potential .........0.5V to VCC+0.5V
DC Voltage Applied to Outputs
in High Z State .........................................0.5V to V_CC+0.5V
DC Input Voltage ..........................................−0.5V to V_CC+0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MILSTD883, Method 3015)
Latch-Up Current..................................................... >200 mA

CY7C4285V Features

• 3.3V operation for low power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO) memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
-I_CC = 30 mA
-I_SB = 4 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin 10x10 STQFP
• Pin-compatible density upgrade to CY7C42X5V-ASC families
• Pin-compatible 3.3V solutions for CY7C4255/65/75/85

CY7C4285V Connection Diagram

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