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CY7C147-25VI, CY7C1472BV33-167AXI, CY7C1472V25

Table of contents:
Info of CY7C147-25VI
Info of CY7C1472BV33-167AXI
Info of CY7C1472V25

CY7C147-25VI, CY7C1472BV33-167AXI, CY7C1472V25 Selling Leads, Datasheet

MFG:Cypress Semiconductor Corp Category:Integrated Circuits (ICs) Package Cooled:N/A D/C:05+

CY7C147-25VI, CY7C1472BV33-167AXI, CY7C1472V25 Picture

CY7C147-25VI, CY7C1472BV33-167AXI, CY7C1472V25 Datasheet download

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Part Number: CY7C147-25VI

Category: Integrated Circuits (ICs)

MFG: Cypress Semiconductor Corp

Package Cooled: N/A

D/C: 05+

Description: IC SRAM 72MB SYNC 100-TQFP

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CY7C1472BV33-167AXI Parameters

Technical/Catalog Information	CY7C1472BV33-167AXI
Vendor	Cypress Semiconductor Corp
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous
Memory Size	72M (4M x 18)
Speed	167MHz
Interface	Parallel
Package / Case	100-TQFP
Packaging	Tray
Voltage - Supply	3.135 V ~ 3.6 V
Operating Temperature	-40°C ~ 85°C
Format - Memory	RAM
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CY7C1472BV33 167AXI CY7C1472BV33167AXI

CY7C1472BV33-167AXI General Description

The CY7C1472BV33-167AXI is a type of synchronous pipelined burst SRAMs.It is designed for supporting infinite true back-to-back read or write operations with no wait states. The CY7C1472BV33-167AXI is equipped with the advan ced logic demanded to enable consecutive read or write operations with data being converted on every clock cycle.T his feature dramatically improves the throughput of data in systems that demand frequent read or write transitions. The CY7C1472BV33-167AXI is pin compatible and functionally equivalent to ZBT devices.

Features of the CY7C1472BV33-167AXI are:(1)pin-compatible and functionally equivalent to ZBT;(2)supports 250 MH z bus operations with zero wait states,available speed grades are 250, 200, and 167 MHz;(3)internally self-timed ou tput buffer control to eliminate the need to use asynchronous OE;(4)fully registered (inputs and outputs) for pipeline d operation;(5)byte write capability;(6)single 3.3V power supply;(7)3.3V/2.5V IO power supply;(8)fast clock-to-outp ut time.

The absolute maximum ratings of the CY7C1472BV33-167AXI can be summarized as:(1):storage temperature ranges from65°C to +150°C;(2):ambient temperature with power applied is55°C to +125°C;(3):supply voltage on VD D relative to GND is0.5V to +4.6V;(4):supply voltage on VDDQ relative to GND is0.5V to +VDD; (5):DC to outputs in tri-state is0.5V to VDDQ + 0.5V;(6):DC input voltage is0.5V to VDD + 0.5V;(7):current into outputs (LOW)is 20 mA;(8):static discharge voltage(MIL-STD-883, Method 3015)is greater than 2001V;(9):latch up current is greater tha n 200 mA.

CY7C1472BV33-167AXI Connection Diagram

CY7C1472V25 General Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with dat
a being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions.
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN</a>) signal,which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BW</a>_aBW</a>_h for CY7C1474V25, BW</a>_aBW</a>_d for CY7C1470V25 and BW</a>_aBW</a>_b for CY7C1472V25) and a Write Enable (WE</a>) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE</a>₁, CE₂, CE</a>₃) and an asynchronous Output Enable (OE</a>) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

CY7C1472V25 Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature ..............................65°C to +150°C
Ambient Temperature with
Power Applied.........................................55°C to +125°C
Supply Voltage on V_DD Relative to GND........0.5V to +3.6V
DC to Outputs in Tri-State..................0.5V to V_DDQ + 0.5V
DC Input Voltage..................................0.5V to V_DD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA

CY7C1472V25 Features

•Pin-compatible and functionally equivalent to ZBT™
•Supports 250-MHz bus operations with zero wait states
-Available speed grades are 250, 200, and 167 MHz
•Internally self-timed output buffer control to eliminate the need to use asynchronous OE</a>
•Fully registered (inputs and outputs) for pipelined operation
•Byte Write capability
•Single 2.5V power supply
•2.5V/1.8V I/O operation
•Fast clock-to-output times
-3.0 ns (for 250-MHz device)
-3.0 ns (for 200-MHz device)
-3.4 ns (for 167-MHz device)
•Clock Enable (CEN</a>) pin to suspend operation
•Synchronous self-timed writes
•CY7C1470V25 and CY7C1472V25 available in lead-free 100 TQFP, and 165 fBGA packages. CY7C1474V25 available in 209-ball fBGA package.
•Compatible with IEEE 1149.1 JTAG Boundary Scan
•Burst capability-linear or interleaved burst order
•"ZZ" Sleep Mode option and Stop Clock option

CY7C1472V25 Connection Diagram

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