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CY7C1420BV18-250BZC, CY7C1421AV18, CY7C142-25LC

Table of contents:
Info of CY7C1420BV18-250BZC
Info of CY7C1421AV18
Info of CY7C142-25LC

CY7C1420BV18-250BZC, CY7C1421AV18, CY7C142-25LC Selling Leads, Datasheet

MFG:Cypress Semiconductor Corp Category:Integrated Circuits (ICs) Package Cooled:BGA D/C:0807/0707

CY7C1420BV18-250BZC, CY7C1421AV18, CY7C142-25LC Picture

CY7C1420BV18-250BZC, CY7C1421AV18, CY7C142-25LC Datasheet download

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Part Number: CY7C1420BV18-250BZC

Category: Integrated Circuits (ICs)

MFG: Cypress Semiconductor Corp

Package Cooled: BGA

D/C: 0807/0707

Description: IC SRAM 1MX36 DDRII 165-FBGA

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CY7C1420BV18-250BZC Parameters

Technical/Catalog Information	CY7C1420BV18-250BZC
Vendor	Cypress Semiconductor Corp
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous
Memory Size	36M (1M x 36)
Speed	250MHz
Interface	Parallel
Package / Case	165-FBGA
Packaging	Tray
Voltage - Supply	1.7 V ~ 1.9 V
Operating Temperature	0°C ~ 70°C
Format - Memory	RAM
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	CY7C1420BV18 250BZC CY7C1420BV18250BZC

CY7C1421AV18 General Description

The CY7C1417AV18, CY7C1428AV18, CY7C1419AV18, and CY7C1421AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II (Double Data Rate) architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with four 8-bit words in the case of CY7C1417AV18 and four 9-bit words in the case of CY7C1428AV18 that burst sequentially into or out of the device. The burst counter always starts with "00" internally in the case of CY7C1417AV18 and CY7C1421AV18. On CY7C1428AV18 and CY7C1419AV18, the burst counter takes in the last two significant bits of the external address and bursts four 18-bit words in the case of CY7C1428AV18, and four 36-bit words in the case of CY7C1419AV18, sequentially into or out of the device.

Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1421AV18 Maximum Ratings

Storage Temperature .................................65°C to +150°C
Ambient Temperature with Power Applied .10°C to +85°C
Supply Voltage on VDD Relative to GND........ 0.5V to +2.9V
DC Applied to Outputs in High-Z......... 0.5V to V_DDQ + 0.3V
DC Input Voltage^[16] ..........................0.5V to V_DDQ + 0.3V
Current into Outputs (LOW)....................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)... > 2001V
Latch-up Current................................................. > 200 mA

CY7C1421AV18 Features

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 300-MHz clock for high bandwidth
• 4-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4VV_DD)
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (D_LL) for accurate data placement

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