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CY7C1308DV25C-167BZCT, CY7C1310AV18, CY7C1310AV18-133BZC

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Info of CY7C1308DV25C-167BZCT
Info of CY7C1310AV18
Info of CY7C1310AV18-133BZC

CY7C1308DV25C-167BZCT, CY7C1310AV18, CY7C1310AV18-133BZC Selling Leads, Datasheet

MFG:Cypress Semiconductor Corp Category:Integrated Circuits (ICs) Package Cooled:BGA D/C:09+

CY7C1308DV25C-167BZCT, CY7C1310AV18, CY7C1310AV18-133BZC Picture

CY7C1308DV25C-167BZCT, CY7C1310AV18, CY7C1310AV18-133BZC Datasheet download

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Part Number: CY7C1308DV25C-167BZCT

Category: Integrated Circuits (ICs)

MFG: Cypress Semiconductor Corp

Package Cooled: BGA

D/C: 09+

Description: IC SRAM 256KX36 SYNC 165-FBGA

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CY7C1308DV25C-167BZCT Parameters

Technical/Catalog Information	CY7C1308DV25C-167BZCT
Vendor	Cypress Semiconductor Corp
Category	Integrated Circuits (ICs)
Memory Type	SRAM - Synchronous
Memory Size	9M (256K x 36)
Speed	167MHz
Interface	-
Package / Case	165-FBGA
Packaging	Tape & Reel (TR)
Voltage - Supply	-
Operating Temperature	0°C ~ 70°C
Format - Memory	RAM
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	CY7C1308DV25C 167BZCT CY7C1308DV25C167BZCT

CY7C1310AV18 General Description

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separateports to access the memory array. The Read port hasdedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write opera-tions. QDR-II architecture has separate data inputs and dataoutputs to completely eliminate the need to "turn-around" thedata bus required with common I/O devices. Access to eachport is accomplished through a common address bus. TheRead address is latched on the rising edge of the K clock andthe Write address is latched on the rising edge of the K clock.

Accesses to the QDR-II Read and Write ports are completelyindependent of one another. In order to maximize datathroughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each addresslocation isassociated with two 8-bit words (CY7C1310AV18) or 18-bitwords (CY7C1312AV18) or 36-bit words (CY7C1314AV18)that burst sequentially into or out of the device. Since data canbe transferred into and out of the device on every rising edgeof both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminatingbus "turn-arounds."Depth expansion is accomplished with Port Selects for eachport. Port selects allow each port to operate independently.All synchronous inputs pass through input registers controlledby the K or K input clocks. All data outputs pass through outputregisters controlled by the C or C (or K or K in a single clockdomain) input clocks. Writes are conducted with on-chip

CY7C1310AV18 Maximum Ratings

Pin Name	I/O	Pin Description
VREF	Input-Reference	Reference Voltage Input . Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.
VDD	Power Supply	Power supply inputs to the core of the device
VSS	Ground	Ground for the device
VDDQ	Power Supply	Power supply inputs for the outputs of the device

CY7C1310AV18 Features

•Separate independent Read and Write data ports-Supports concurrent transactions
•167-MHz clock for high bandwidth
•2-Word Burst on all accesses
•Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167MHz
•Two input clocks (K and K) for precise DDR timing-SRAM uses rising edges only
•Two output clocks (C and C) account for clock skew and flight time mismatching
•Echo clocks (CQ and CQ) simplify data capture in high speed systems
•Single multiplexed address input bus latches address inputs for both Read and Write ports
•Separate Port Selects for depth expansion
•Synchronous internally self-timed writes
•Available in x8, x18, and x36 configurations
•Full data coherancy , providing most current data
•Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd
•13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball (11x15 matrix)
•Variable drive HSTL output buffers
•JTAG 1149.1 compatible test access port

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