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CY7C1302V25, CY7C1302V25-100BZC, CY7C1302V25-100BZCT

Table of contents:
Info of CY7C1302V25
Info of CY7C1302V25-100BZC
Info of CY7C1302V25-100BZCT

CY7C1302V25, CY7C1302V25-100BZC, CY7C1302V25-100BZCT Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:BGA D/C:08+09+

CY7C1302V25, CY7C1302V25-100BZC, CY7C1302V25-100BZCT Picture

CY7C1302V25, CY7C1302V25-100BZC, CY7C1302V25-100BZCT Datasheet download

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Part Number: CY7C1302V25

MFG: CYPRESS

Package Cooled: BGA

D/C: 08+09+

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CY7C1302V25 General Description

The CY7C1302V25 is a 2.5V Synchronous-Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common I/O devices. Accesses to the CY7C1302V25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C) thereby maximizing performance while simplifying system design.

Depth expansion is accomplished with a Port Select input for each port. Each Port Selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1302V25 Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................65C to +150C
Ambient Temperature with
Power Applied ...........................................55C to +125C
Supply Voltage on VDD Relative to GND.... 0.5V to +3.6V
DC Voltage Applied to Outputs
in High Z State^[12] ..........................0.5V to V_DDQ + 0.5V
DC Input Voltage^[12] ......................0.5V to V_DDQ + 0.5V
Current into Outputs (LOW).................................... 20 mA
Static Discharge Voltage .......................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................>200 mA

CY7C1302V25 Features

• Separate Independent Read and Write Data Ports
   -Supports concurrent transactions
• 167-MHz Clock for High Bandwidth
   -2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
   -SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew and flight time mis-matches
• Single multiplexed address input bus latches address inputs for both READ and WRITE ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13x15 mm - 1.0 mm pitch FBGA package, 165 ball (11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V-1.9V)
• JTAG Interface
• Variable Impedance HSTL

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