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CY7C057V, CY7C057V-12AC706, CY7C057V-12ACT

Table of contents:
Info of CY7C057V
Info of CY7C057V-12AC706
Info of CY7C057V-12ACT

CY7C057V, CY7C057V-12AC706, CY7C057V-12ACT Selling Leads, Datasheet

MFG:N/A Package Cooled:N/A D/C:09+

CY7C057V, CY7C057V-12AC706, CY7C057V-12ACT Picture

CY7C057V, CY7C057V-12AC706, CY7C057V-12ACT Datasheet download

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Part Number: CY7C057V

MFG: N/A

Package Cooled: N/A

D/C: 09+

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CY7C057V General Description

The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE)[3], Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic Power-Down feature is controlled independently on each port by Chip Select (CE0 and CE1) pins.

The CY7C056V and CY7C057V are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array (BGA) packages.

CY7C057V Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied............................................55°C to +125°C
Supply Voltage to Ground Potential ............... ..0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................0.5V to VDD+0.5V
DC Input Voltage.................................. 0.5V to VDD+0.5V^[7]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
Latch-Up Current.................................................... >200 mA

CY7C057V Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
- Active: I_CC = 250 mA (typical)
- Standby: I_SB3 = 10 A (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device
• On-Chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 144-Pin TQFP or 172-Ball BGA
• Pb-Free packages available
• Compact packages:
- 144-Pin TQFP (20 x 20 x 1.4 mm)
- 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)

CY7C057V Connection Diagram

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