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CY7C009V, CY7C009V-15AI, CY7C009V-15AXI

Table of contents:
Info of CY7C009V
Info of CY7C009V-15AI
Info of CY7C009V-15AXI

CY7C009V, CY7C009V-15AI, CY7C009V-15AXI Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:N/A D/C:09+

CY7C009V, CY7C009V-15AI, CY7C009V-15AXI Picture

CY7C009V, CY7C009V-15AI, CY7C009V-15AXI Datasheet download

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Part Number: CY7C009V

MFG: CYPRESS

Package Cooled: N/A

D/C: 09+

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CY7C009V General Description

The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin.

The CY7C008V/009V and CY7018V/019V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP).

CY7C009V Maximum Ratings

(Above which the useful life may be impaired. For user guidelines,not tested.)
Storage Temperature ............................65°C to +150°C
Ambient Temperature with
Power Applied........................................55°C to +125°C
Supply Voltage to Ground Potential .............0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State..........................0.5V to V_CC+0.5V
DC Input Voltage ...................................0.5V to V_CC+0.5V
Output Current into Outputs (LOW)........................... 20 mA
Static Discharge Voltage.......................................... >1100V
Latch-Up Current.................................................... >200 mA

CY7C009V Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
- Active: ICC = 115 mA (typical)
- Standby: ISB3 = 10 A (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
• Pb-Free packages available

CY7C009V Connection Diagram

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