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CY7C007A-20JXC, CY7C007A-25JC, CY7C007AV

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Info of CY7C007A-20JXC
Info of CY7C007A-25JC
Info of CY7C007AV

CY7C007A-20JXC, CY7C007A-25JC, CY7C007AV Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:PLCC D/C:08+

CY7C007A-20JXC, CY7C007A-25JC, CY7C007AV Picture

CY7C007A-20JXC, CY7C007A-25JC, CY7C007AV Datasheet download

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Part Number: CY7C007A-20JXC

MFG: CYPRESS

Package Cooled: PLCC

D/C: 08+

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CY7C007AV General Description

The CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and 32K x8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are pro-vided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be uti- lized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S</a> pin is provid-ed for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interpro-cessor/multiprocessor designs, communications status buffer-ing, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE</a>),Read or Write Enable (R/W</a>), and Output Enable (OE</a>). Twoflags are provided on each port (BUSY</a> and INT</a>). BUSY</a> sig-nals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT</a>) per-mits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token,from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared re-source is in use. An automatic power-down feature is con-trolled independently on each port by a Chip Select (CE</a>) pin.

CY7C007AV Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage to Ground Potential..................0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State..............................0.5V to V_CC+0.5V
DC Input Voltage^[11]..................................0.5V to V_CC+0.5V
Output Current into Outputs (LOW)................................20 mA
Static Discharge Voltage.............................................. >2001V
Latch-Up Current....................................................... >200 mA

CY7C007AV Features

•True Dual-Ported memory cells which allow simulta-neous access of the same memory location
•4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV)
•4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV)
•0.35-micron CMOS for optimum speed/power
•High-speed access: 20/25 ns
•Low operating power
-Active: I_CC = 115 mA (typical)
-Standby: I_SB3 = 10 µA (typical)
•Fully asynchronous operation
•Automatic power-down
•Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device
•On-chip arbitration logic
•Semaphores included to permit software handshaking between ports
•INT</a> flag for port-to-port communication
•Pin select for Master or Slave
•Commercial and Industrial Temperature Ranges
•Available in 68-pin PLCC (all) and 64-pin TQFP (7C006AV & 7C144AV)
•Pin-compatible and functionally equivalent to IDT70V05, 70V06, and 70V07.

CY7C007AV Connection Diagram

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