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CY2SSTV857-32, CY2SSTV8575AC, CY2SSTV857ZC-27T

Table of contents:
Info of CY2SSTV857-32
Info of CY2SSTV8575AC
Info of CY2SSTV857ZC-27T

CY2SSTV857-32, CY2SSTV8575AC, CY2SSTV857ZC-27T Selling Leads, Datasheet

MFG:CYPRESS Package Cooled:N/A D/C:09+

CY2SSTV857-32, CY2SSTV8575AC, CY2SSTV857ZC-27T Picture

CY2SSTV857-32, CY2SSTV8575AC, CY2SSTV857ZC-27T Datasheet download

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Part Number: CY2SSTV857-32

MFG: CYPRESS

Package Cooled: N/A

D/C: 09+

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CY2SSTV857-32 General Description

The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857-32 to be used as a zero delay buffer.

When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs.

CY2SSTV857-32 Maximum Ratings

Input Voltage Relative to V_SS:...............................V_SS 0.3V
Input Voltage Relative to V_DDQ or AV_DD: ...........V_DDQ+ 0.3V
Storage Temperature: ................................65°C to + 150°C
Operating Temperature: ................................40°C to +85°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
V_SS < (Vin or Vout) < V_DDQ.
Unused inputs must always be tied to an appropriate logic
voltage level (either V_SS or V_DDQ).

CY2SSTV857-32 Features

• Operating frequency: 60 MHz to 230 MHz
• Supports 400-MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of 40°C to 85°C
• Conforms to JEDEC DDR specification

CY2SSTV857-32 Connection Diagram

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