CV123PV, CV125PA, CV125PAG Selling Leads, Datasheet
MFG:IDT Package Cooled:SSOP-7.2-56P D/C:04+
CV123PV, CV125PA, CV125PAG Datasheet download
Part Number: CV123PV
MFG: IDT
Package Cooled: SSOP-7.2-56P
D/C: 04+
CV123PV, CV125PA, CV125PAG
- Table of contents:
Info of CV123PV
Info of CV125PA
Info of CV125PAG
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About CV10440
PDF/DataSheet Download
Datasheet: CV10440
File Size: 14099 KB
Manufacturer: SEME-LAB [Seme LAB]
Download : Click here to Download
About CV10440
PDF/DataSheet Download
Datasheet: CV10440
File Size: 14099 KB
Manufacturer: SEME-LAB [Seme LAB]
Download : Click here to Download
About CV10440
PDF/DataSheet Download
Datasheet: CV10440
File Size: 14099 KB
Manufacturer: SEME-LAB [Seme LAB]
Download : Click here to Download
CV123PV General Description
PC CLOCK
IDTCV123 is a 56 pin clock device. The CPU output buffer is designed tosupport up to 400MHz processor. This chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for SerialATA clock provides high accuracy frequency. This device also implementsBand-gap referenced IREF to reduce the impact of VDD variation on differentialoutputs, which can provide more robust system performance.Static PLL frequency divide error can be as low as 36 ppm, worse case 114ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clockhas its own Spread Spectrum selection, which allows for isolated changesinstead of affecting other clock groups.
IDTCV123 is a 56 pin clock device. The CPU output buffer is designed tosupport up to 400MHz processor. This chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for SerialATA clock provides high accuracy frequency. This device also implementsBand-gap referenced IREF to reduce the impact of VDD variation on differentialoutputs, which can provide more robust system performance.Static PLL frequency divide error can be as low as 36 ppm, worse case 114ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clockhas its own Spread Spectrum selection, which allows for isolated changesinstead of affecting other clock groups.
CV123PV Maximum Ratings
CV125PAG General Description
PC CLOCK
IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M andCKSSCD requirements, for Intel advance P4 processors. The CPU outputbuffer is designed to support up to 400MHz processor. This chip has four PLLsinside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This devicealso implements Band-gap referenced IREF to reduce the impact of VDD variationon differential outputs, which can provide more robust system performance.Static PLL frequency divide error can be as low as 36 ppm, worse case 114ppm, providing high accuracy output
IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M andCKSSCD requirements, for Intel advance P4 processors. The CPU outputbuffer is designed to support up to 400MHz processor. This chip has four PLLsinside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This devicealso implements Band-gap referenced IREF to reduce the impact of VDD variationon differential outputs, which can provide more robust system performance.Static PLL frequency divide error can be as low as 36 ppm, worse case 114ppm, providing high accuracy output
CV125PAG Maximum Ratings
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