MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:DIP16 D/C:98+
CD74HCT190E, CD74HCT191MG4, CD74HCT193 Datasheet download
Category: Integrated Circuits (ICs)
MFG: Texas Instruments
Package Cooled: DIP16
D/C: 98+
Description: IC SYNC 4-BIT UP/DN CNTR 16SOIC
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PDF/DataSheet Download
Datasheet: CD7232CS
File Size: 342887 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: CD7232CS
File Size: 342887 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: CD74HCT193
File Size: 314376 KB
Manufacturer: TI
Download : Click here to Download
| Technical/Catalog Information | CD74HCT191MG4 |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Logic Type | Binary Counter |
| Trigger Type | Positive Edge |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Number of Bits per Element | 4 |
| Number of Elements | 1 - Single |
| Direction | Up, Down |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (3.9mm Width) |
| Reset | - |
| Packaging | Tube |
| Operating Temperature | -55°C ~ 125°C |
| Count Rate | 30MHz |
| Timing | Synchronous |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | CD74HCT191MG4 CD74HCT191MG4 |
The 'HC192, 'HC193 and 'HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock- Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
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