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CD74HC161, CD74HC161M, CD74HC161M96

Table of contents:
Info of CD74HC161
Info of CD74HC161M
Info of CD74HC161M96

CD74HC161, CD74HC161M, CD74HC161M96 Selling Leads, Datasheet

MFG:Texas Instruments (VA) Category:Integrated Circuits (ICs) Package Cooled:DIP D/C:98

CD74HC161, CD74HC161M, CD74HC161M96 Datasheet download

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Part Number: CD74HC161M

Category: Integrated Circuits (ICs)

MFG: Texas Instruments (VA)

Package Cooled: DIP

D/C: 98

Description: IC PRESET SYNC COUNTER 16-SOIC

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CD74HC161 General Description

The 'HC161, 'HCT161, 'HC163, and 'HCT163 are presettable synchronous counters that feature look-ahead carry logic for use in high-speed counting applications. The 'HC161 and 'HCT161 are asynchronous reset decade and binary counters, respectively; the 'HC163 and 'HCT163 devices are decade and binary counters, respectively, that are reset synchronously with the clock. Counting and parallel presetting are both accomplished synchronously with the negative-to-positive transition of the clock.

A low level on the synchronous parallel enable input, SPE, disables counting operation and allows data at the P0 to P3 inputs to be loaded into the counter (provided that the setup and hold requirements for SPE are met).

All counters are reset with a low level on the Master Reset input, MR. In the 'HC163 and 'HCT163 counters (synchronous reset types), the requirements for setup and hold time with respect to the clock must be met.

Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the 'HC161 and 'HCT161 types).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.

The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.

CD74HC161 Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I_IK
   For V_I< -0.5V or V_I> V_CC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
   For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I_O
   For -0.5V < V_O < V_CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I_O
   For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC V_CC or Ground Current, I_CC . . . . . . . . . . . . . . . . . . . . .. . . .±50mA

CD74HC161 Features

• 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset
• 'HC163, 'HCT163 4-Bit Binary Counter, Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility, V_IL= 0.8V (Max), V_IH = 2V (Min)
   - CMOS Input Compatibility, I_l 1A at V_OL, V_OH

CD74HC161 Connection Diagram

CD74HC161M Parameters

Technical/Catalog Information	CD74HC161M
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Logic Type	Binary Counter
Trigger Type	Negative Edge
Voltage - Supply	2 V ~ 6 V
Number of Bits per Element	4
Number of Elements	1 - Single
Direction	Up
Mounting Type	Surface Mount
Package / Case	16-SOIC (3.9mm Width)
Reset	Asynchronous
Packaging	Tube
Operating Temperature	-55°C ~ 125°C
Count Rate	24MHZ
Timing	Synchronous
Drawing Number	296; 4040047-4; D; 16
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CD74HC161M CD74HC161M

CD74HC161M General Description

Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the 'HC161 and 'HCT161 types).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count.

The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage.

CD74HC161M Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . .. . . . . -0.5V to 7V
DC Input Diode Current, I_IKFor VI < -0.5V or VI > V_CC + 0.5V . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For VO < -0.5V or VO > V_CC + 0.5V . . . . . . . . . . .. . . . . . .±20mA
DC Drain Current, per Output, I_OFor -0.5V < VO < V_CC + 0.5V. . . . . . . . . . . . . . . . . . .. . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < V_CC + 0.5V . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I_CC . . . . . . . . . . . . . . . . . . . . .±50mA

CD74HC161M Features

• 'HC161, 'HCT161 4-Bit Binary Counter, Asynchronous Reset
• 'HC163, 'HCT163 4-Bit Binary Counter, Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH

CD74HC161M Connection Diagram

CD74HC161M96 Parameters

Technical/Catalog Information	CD74HC161M96
Vendor	Texas Instruments (VA)
Category	Integrated Circuits (ICs)
Logic Type	Binary Counter
Trigger Type	Negative Edge
Voltage - Supply	2 V ~ 6 V
Number of Bits per Element	4
Number of Elements	1 - Single
Direction	Up
Mounting Type	Surface Mount
Package / Case	16-SOIC (3.9mm Width)
Reset	Asynchronous
Packaging	Cut Tape (CT)
Operating Temperature	-55°C ~ 125°C
Count Rate	24MHZ
Timing	Synchronous
Drawing Number	296; 4040047-4; D; 16
Lead Free Status	Contains Lead
RoHS Status	RoHS Non-Compliant
Other Names	CD74HC161M96 CD74HC161M96 296 23206 1 ND 296232061ND 296-23206-1

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