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CD74ACT112M, CD74ACT138, CD74ACT138M

Table of contents:
Info of CD74ACT112M
Info of CD74ACT138
Info of CD74ACT138M

CD74ACT112M, CD74ACT138, CD74ACT138M Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:9232 D/C:150

CD74ACT112M, CD74ACT138, CD74ACT138M Datasheet download

Five Points

Part Number: CD74ACT112M

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: 9232

D/C: 150

Description: IC DUAL JK NEG-EDG-TRG FF 16SOIC

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CD74ACT112M Parameters

Technical/Catalog Information	CD74ACT112M
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Mounting Type	Surface Mount
Package / Case	16-SOIC (3.9mm Width)
Function	Set and Reset
Number of Bits per Element	1
Number of Elements	2 - Dual
Current - Output High, Low	24mA, 24mA
Output Type	Differential
Trigger Type	Negative Edge
Type	JK Type
Packaging	Tube
Operating Temperature	-55°C ~ 125°C
Delay Time - Propagation	2.6ns
Frequency - Clock	100MHz
Voltage - Supply	4.5 V ~ 5.5 V
Drawing Number	296; 4040047-4; D; 16
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	CD74ACT112M CD74ACT112M

CD74ACT138 Parameters

CD74ACT138 Features

Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74ACT138 General Description

3-Line to 8-Line Inverting Decoders/Demultiplexers

CD74ACT138 Maximum Ratings

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O> -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . . .±50mA
DC V_CC or Ground Current, I_CC or I_GND (Note 5) . . . . . . . .±100mA

CD74ACT138 Features

Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

CD74ACT138 Typical Application

CD74ACT138 Datasheet

CD74ACT138 Connection Diagram

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