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AS7C33512NTF18, AS7C33512PFD18A, AS7C33512PFD36

Table of contents:
Info of AS7C33512NTF18
Info of AS7C33512PFD18A
Info of AS7C33512PFD36

AS7C33512NTF18, AS7C33512PFD18A, AS7C33512PFD36 Selling Leads, Datasheet

MFG:ALLANCE Package Cooled:TQFP D/C:05+

AS7C33512NTF18, AS7C33512PFD18A, AS7C33512PFD36 Picture

AS7C33512NTF18, AS7C33512PFD18A, AS7C33512PFD36 Datasheet download

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Part Number: AS7C33512NTF18

MFG: ALLANCE

Package Cooled: TQFP

D/C: 05+

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AS7C33512PFD18A General Description

The AS7C33512PFD18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Fast cycle times of 6/7.5 ns with clock access times (t_CD) of 3.5/3.8 ns enable 166 MHz and 133 MHz bus frequencies . Three chip enable inputs permit easy memory expansinon. Burst operation is initiated in one of two ways: the controller strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequnet internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data when ADSP accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven is ignored on the clock edge that samples ADSP asserted, but it is sampled on all on the output pins on the next positive edge of CLK.ADV is sampled LOW and both address subsequent clock edges. Address is incremented internally for the next access of the burst when ADVstrobes are HIGH. Burst mode is selectable with theLBOinput. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers withOEand asserting a write command. A global write enable GWE writes all 18bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is when BWn incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in double-cycle deselect feature during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows:

·ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
·WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
·Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging.

AS7C33512PFD18A Maximum Ratings

Parameter	Symbol	Min	Max	Unit
Power supply voltage relative to GND	V_DD, V_DDQ	0.5	+4.6	V
Input voltage relative to GND (input pins)	V_IN	0.5	V_DD+ 0.5	V
Input voltage relative to GND (I/O pins)	V_IN	0.5	V_DDQ+ 0.5	V
Power dissipation	P_D		1.8	W
DC output current	I_OUT		50	mA
Storage temperature (plastic)	T_stg	65	+150
Temperature under bias	T_bias	65	+135

1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.

AS7C33512PFD18A Features

• Organization: 524,288 words × 18 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Asynchronous output enable control
• Individual byte write and global write
• Available in 100-pin TQFP package
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ

AS7C33512PFD18A Connection Diagram

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