AD9885KSTZ-110, AD9886, AD9886-140 Selling Leads, Datasheet
MFG:AD Package Cooled:QFP80 D/C:05+Pb
AD9885KSTZ-110, AD9886, AD9886-140 Datasheet download
Part Number: AD9885KSTZ-110
MFG: AD
Package Cooled: QFP80
D/C: 05+Pb
AD9885KSTZ-110, AD9886, AD9886-140
- Table of contents:
Info of AD9885KSTZ-110
Info of AD9886
Info of AD9886-140
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About AD9000
PDF/DataSheet Download
Datasheet: AD9000
File Size: 210792 KB
Manufacturer: AD [Analog Devices]
Download : Click here to Download
About AD9886
PDF/DataSheet Download
Datasheet: AD9886
File Size: 254431 KB
Manufacturer: AD [Analog Devices]
Download : Click here to Download
About AD9000
PDF/DataSheet Download
Datasheet: AD9000
File Size: 210792 KB
Manufacturer: AD [Analog Devices]
Download : Click here to Download
AD9886 General Description
The AD9886 is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140MSPS encode rate capability and full-power analog bandwidth of 330MHz supports resolutions up to SXGA (1280 * 1024 at 75 Hz).
For ease of design and to minimize cost, the AD9886 is a fully integrated interface solution for FPDs. The AD9886 includes a 140 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from an HSYNC, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and an HSYNC signal. Three-state CMOS outputs may be powered from 2.5V to 3.3V. The AD9886's on-chip PLL generates a pixel clock from an HSYNC. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC.
A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9886 also offers full sync processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully pro-grammable via a 2-wire serial interface.
AD9886 Maximum Ratings
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature . . . . . . . . . . . 25°C to +85°C
Storage Temperature . . . . . . . . . . . . .65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . 150°C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature . . . . . . . . . . . 25°C to +85°C
Storage Temperature . . . . . . . . . . . . .65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . 150°C
AD9886 Features
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp for YUV Applications
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp for YUV Applications
AD9886 Connection Diagram
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