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The VCXR162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to-LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-LOW. When OEAB is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.
The 74VCXR162601 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCXR162601 is also designed with 26W series resistors on both the A and B Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.
· 1.2V to 3.6V VCC supply operation · 3.6V tolerant inputs and outputs · tPD(A to B, B to A) 3.8 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC · Power-off high impedance inputs and outputs · Static Drive (IOH/IOL) ±12 mA @ 3.0V VCC ±8 mA @ 2.3V VCC ±3 mA @ 1.65V VCC · Uses patented Quiet Seriesä noise/EMI reduction circuitry · Latchup performance exceeds JEDEC 78 conditions · ESD performance: Human body model > 2000V Machine model > 200V