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The VCX162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state.
The VCX162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/ transmitters.
The 74VCX162835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX162835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
· 1.2V to 3.6V VCC supply operation · 3.6V tolerant inputs and outputs · tPD 4.2ns max for 3.0V to 3.6V VCC 5.2ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC · Power-off high impedance inputs and outputs · Static Drive (IOH/IOL) ±12mA @ 3.0V VCC ±8 mA @ 2.3V VCC ±3 mA @ 1.65V VCC · Uses patented Quiet Seriesä noise/EMI reduction circuitry · Latchup performance exceeds JEDEC 78 conditions · ESD performance: Human body model > 2000V Machine model > 200V