Position: Home > DataSheet > Index 7 > 74H Series > 74HC190, 74HC190N, 74HC191

Low Cost Custom Prototype PCB Manufacturer

74HC190, 74HC190N, 74HC191

Table of contents:
Info of 74HC190
Info of 74HC190N
Info of 74HC191

74HC190, 74HC190N, 74HC191 Selling Leads, Datasheet

MFG:412 Package Cooled:HIT D/C:DIP

74HC190, 74HC190N, 74HC191 Datasheet download

Five Points

Part Number: 74HC190

MFG: 412

Package Cooled: HIT

D/C: DIP

Attentive hint

Want to post a buying lead? If you are not a member yet, please select the specific/related part number first and then fill the quantity and your contact details in the "Request for Quotation Form" on the left, and then click "Send RFQ".Your buying lead can then be posted, and the reliable suppliers will quote via our online message system or other channels soon.

How to buy ?

How long will receive a response.

Top Sellers:

TOP

74HC190 General Description

The 74HC/HCT190 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT190 are asynchronously presettable up/down BCD decade counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D₀to D₃) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting function.

Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH.

Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches "9" in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding
spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Figs 5 and 6.

In Fig.5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse as indicated in the function table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications.

Fig.6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the clock.

In Fig.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Figs 5 and 6 does not apply.

74HC190 Features

· Synchronous reversible counting
· Asynchronous parallel load
· Count enable control for synchronous expansion
· Single up/down control input
· Output capability: standard
· I_CC category: MSI

74HC190 Connection Diagram

74HC191 General Description

The 74HC191 is designed as high-speed si-gate CMOS devices and are pin compatible with low power schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. It is asynchronously presettable 4-bit binary up/down counters and it contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

It has six features. The first one is synchronous reversible counting. The second one is asynchronous parallel load. The third one is count enable control for synchronous expansion. The fourth one is single up/down control input. The fifth one is its output capability would be standard. The sixth one is its ICC category would be MSI. That are all the main features.

Some important AC characteristics and specifications have been concluded into several points as follow.For Tamb=25°C the first one is about its propagation delay CP to Qn which would be typ 72ns and max 220ns at Vcc=2.0V and would be typ 26ns and max 44ns at Vcc=4.5V and would be typ 21ns and max 37ns at Vcc=6.0V. The second one is about its propagation delay CP to TC which would be typ 83ns and max 255ns at Vcc=2.0V and typ 30ns and max 51ns at Vcc=4.5V and would be typ 24ns and max 43ns at Vcc=6.0V. The third one is about its output transition time which would be typ 19ns and max 75ns at Vcc=2.0V and typ 7ns and max 15ns at Vcc=4.5V and would be typ 6ns and max 13ns at Vcc=6.0V.

Also for the Tamb range of -40 to +125°C the first one is about its propagation delay An to Yn which would be max 330ns at Vcc=2.0V and would be max 66ns at Vcc=4.5V and would be max 56ns at Vcc=6.0V. The second one is about its propagation delay E3 to Yn which would be max 395ns at Vcc=2.0V and max 77ns at Vcc=4.5V and would be max 65ns at Vcc=6.0V. The third one is about its output transition time which would be max 110ns at Vcc=2.0V and max 22ns at Vcc=4.5V and would be max 19ns at Vcc=6.0V. And so on. For more information please contact us.

74HC191 Maximum Ratings

74HC191 Features

Hotspot Suppliers Product

Product List A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 0 1 2 3 4 5 6 7 8 9

MT58L64L18CT-10

Price: 4-6 USD

MT58L64L18CT-10 TQFP100
DL-7140-211M

Price: 5-6.5 USD

DL-7140-211M laser tube
74LVC74APG

Price: 4-5 USD

74LVC74APG - IC FLIP FLOP D-Type POS-EDG DUAL 14TSSOP
CY28346ZI-2

Price: 6.5-8 USD

CYPRESS - Clock Synthesizer with Differential CPU Outputs
PI5V330QEX

Price: 0.284-0.286 USD

PI5V330QEX Pericom Multiplexer Switch ICs
BSM300GA120DN2

Price: 1-2 USD

IGBT power module, Single switch, 1200 V, Collector-emitter voltage, 430A
SVA150XG04TB

Price: 1-2 USD

a-Si TFT-LCD, NEC, 228.096Hmm, 560V
PC354N1

Price: 0.124-0.2 USD

PC354N1T - Mini-flat Package, AC Input Type Photocoupler - Sharp Electrionic Components
RL1210JR-070R22L

Price: 0.177-0.178 USD

RL1210JR51-XX-BL - Thick Film Chip Resistor Low Ohmic - TAITRON Components Incorporated
STPS140A

Price: 0.053-0.055 USD

STPS140A - POWER SCHOTTKY RECTIFIER - STMicroelectronics
STA013

Price: 1.45-1.5 USD

STA013 - MPEG 2.5 LAYER III AUDIO DECODER - STMicroelectronics
SMBJ5347B

Price: 0.073-0.075 USD

SMBJ5347B - 5 Watt Surface Mount Silicon Zener Diodes - Micro Commercial Components