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74AC11002D, 74AC11002DR, 74AC11004

Table of contents:
Info of 74AC11002D
Info of 74AC11002DR
Info of 74AC11004

74AC11002D, 74AC11002DR, 74AC11004 Selling Leads, Datasheet

MFG:T.I Package Cooled:26 D/C:08.09+

74AC11002D, 74AC11002DR, 74AC11004 Picture

74AC11002D, 74AC11002DR, 74AC11004 Datasheet download

Five Points

Part Number: 74AC11002D

MFG: T.I

Package Cooled: 26

D/C: 08.09+

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74AC11004 Parameters

74AC11004 Features

Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)

74AC11004 General Description

Hex Inverters

74AC11004 Maximum Ratings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, I_IK(V_I < 0 or V_I > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O(V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at T_A= 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.6 W
                                                                                                           DB package . . . . . . . . . . . . . . . . . . . 0.6 W
                                                                                                           N package . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are bserved.
              2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.

74AC11004 Features

Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)

74AC11004 Typical Application

74AC11004 Datasheet

74AC11004 Connection Diagram

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