4088, 40882, 40889 Selling Leads, Datasheet
MFG:95+ Package Cooled:QFN-14 D/C:NO
MFG:95+ Package Cooled:QFN-14 D/C:NO
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Datasheet: 4081
File Size: 138531 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: 4081
File Size: 138531 KB
Manufacturer:
Download : Click here to Download
PDF/DataSheet Download
Datasheet: 4081
File Size: 138531 KB
Manufacturer:
Download : Click here to Download
The IDT70V38 is a high-speed 64K x 18 Dual-Port Static RAM. The IDT70V38 is designed to be used as a stand-alone 1152K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 440mW of power.
The IDT70V38 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Symbol |
Rating |
Commercial
& Industrial |
Unit |
VTERM |
Terminal Voltage with respect to GND |
-0.5 to +4.6 |
V |
VTER(2) |
Terminal Voltage |
-55 to +125 |
°C |
TSTG |
Temperature Under Bias |
-65 to +150
|
°C |
IOUT |
DC Output Current |
50
|
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.