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405GP, 405-J50, 4060

Table of contents:
Info of 405GP
Info of 405-J50
Info of 4060

405GP, 405-J50, 4060 Selling Leads, Datasheet

MFG:IBM Package Cooled:BGA D/C:08+/09+

405GP, 405-J50, 4060 Datasheet download

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Part Number: 405GP

MFG: IBM

Package Cooled: BGA

D/C: 08+/09+

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405GP General Description

Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements.

This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.

Technology: IBM CMOS SA-12E, 0.25 m (0.18 m L_eff)

Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA) Power (typical): 1.5W at 200MHz, 2W at 266MHz

405GP Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device

Characteristic	Symbol	Value	Unit
Supply Voltage (Internal Logic)	V_DD	0 to +2.7	V
Supply Voltage (I/O Interface)	OV_DD	0 to +3.6	V
PLL Supply Voltage	AV_DD	0 to +2.7	V
Input Voltage (2.5V CMOS receivers)	V_IN	-0.6 to V_DD + 0.6	V
Input Voltage (3.3V LVTTL receivers)	V_IN	-0.6 to OV_DD + 0.6	V
Input Voltage (5.0V LVTTL receivers)	V_IN	-0.6 to OV_DD + 2.4	V
Storage Temperature Range	T_STG	-55 to +150	°C
Case temperature under bias	T_C	-40 to +120	°C

Note: All specified voltages are with respect to GND.

405GP Features

• IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and external peripherals
- Up to eight devices
- External Mastering supported
• DMA support for external peripherals, internal UART and memory
- Scatter-gather chaining supported
- Four channels
• PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
- Synchronous or asynchronous PCI Bus interface
- Use internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII)
• Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive nterrupts
• Programmable timers
• Two serial ports (16550 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at SDRAM interface frequency
• Supports PowerPC processor boot from PCI memory

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