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40595, 4059BT, 405CR

Table of contents:
Info of 40595
Info of 4059BT
Info of 405CR

40595, 4059BT, 405CR Selling Leads, Datasheet

MFG:HAR / RCA Package Cooled:ph D/C:08+

40595, 4059BT, 405CR Datasheet download

Five Points

Part Number: 40595

MFG: HAR / RCA

Package Cooled: ph

D/C: 08+

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405CR General Description

The IBM PowerPC 405CR^TMis a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications.

This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while providing a base for custom chip designs.

The controller is powered by a PPC405 embedded core. This core tightly couples a 266-MHz CPU, MMU, I- and D-cache, and debug logic. Fine-tuning of the core reduces data transfer overhead, minimizes pipeline stalls, and greatly improves performance.

The PPC405CR employs the IBM CoreConnect^TMbus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 100-MHz Processor Local Bus (PLB) and a 32-bit, 50-MHz On-Chip Peripheral Bus (OPB).High-performance peripherals attach to the PLB; and less performance-critical peripherals attach to the OPB.

Technology: IBM CMOS SA12E 0.25 m (0.18 m L_eff)

Package: 27mm, 316-ball enhanced plastic ball grid array (E-PBGA)

Power (estimated): Typical 0.9W, Maximum 2.0W

405CR Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device

Characteristic	Symbol	Value	Unit
Supply Voltage (Internal Logic)	V_DD	0 to 2.7	V
Supply Voltage (I/O Interface)	OV_DD	0 to 3.6	V
PLL Supply Voltage	AV_DD	0 to 2.7	V
Input Voltage (3.3V LVTTL receivers)	V_IN	0 to 3.6	V
Input Voltage (5.0V LVTTL receivers)	V_IN	0 to 5.5	V
Storage Temperature Range	T_STG	-55 to 150	°C
Case temperature under bias	T_C	-40 to 120	°C

405CR Features

• IBM PowerPC^TM 405 32-bit RISC processor core operating up to 266MHz
- Memory Management Unit
- 16KB instruction and 8KB data caches
- Multiply-Accumulate (MAC) function, including fast multiply unit
- Programmable Timers
- Supports JTAG for board level testing
• PC-100 Synchronous DRAM (SDRAM) interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
• External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and external peripherals
- Up to eight devices
- External Mastering supported
• DMA support for external peripherals, internal UART and memory
- Scatter-gather chaining supported
- Four channels
• Programmable Interrupt Controller supports interrupts from a variety of sources
- Supports 7 external and 10 internal interrupts
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor core
- Programmable critical interrupt priority ordering
- Programmable critical interrupt vector for faster vector processing
• Two serial ports (16550 compatible UART)
• One IIC (I²C) interface
• General Purpose I/O (GPIO) available
• Internal Processor Local Bus (PLB) runs at SDRAM interface frequency

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