100398PC, 100398QCX, 100398QI Selling Leads, Datasheet
MFG:Fairchild Package Cooled:STOCK D/C:91
100398PC, 100398QCX, 100398QI Datasheet download
Part Number: 100398PC
MFG: Fairchild
Package Cooled: STOCK
D/C: 91
100398PC, 100398QCX, 100398QI
- Table of contents:
Info of 100398PC
Info of 100398QCX
Info of 100398QI
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About 100398PC
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Datasheet: 100398PC
File Size: 120708 KB
Manufacturer: FAIRCHILD [Fairchild Semiconductor]
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About 100/200
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Datasheet: 100/200
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Manufacturer: ETC [ETC]
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About 100398QI
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Datasheet: 100398QI
File Size: 120708 KB
Manufacturer: FAIRCHILD [Fairchild Semiconductor]
Download : Click here to Download
100398PC General Description
The 100398 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100398 is ideal for mixed technology applications utilizing either an ECL or TTL backplane.
The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100398 accepts TTL logic levels. A TTL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. A TTL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch transparent.
The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.
The 100398 is designed with FASTTM TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All Inputs have 50 kΩ pull-down resistors.
100398PC Maximum Ratings
Storage Temperature (TSTG)............. −65°C to +150°C
Maximum Junction Temperature
(TJ)............................................................... +150°C
VEE Pin Potential to Ground Pin .............−7.0V to +0.5V
VTTL Pin Potential to Ground Pin ...........−0.5V to +6.0V
ECL Input Voltage (DC)............................. VEE to +0.5V
ECL Output Current
(DC Output HIGH) .........................................−50 mA
TTL Input Voltage (Note 7).................... −0.5V to +7.0V
TTL Input Current (Note 7) .............−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State
3-STATE Output................................. −0.5V to +5.5V
Current Applied to TTL
Output in LOW State (Max) twice the Rated IOL (mA)
ESD (Note 6) .....................................................2000V
Maximum Junction Temperature
(TJ)............................................................... +150°C
VEE Pin Potential to Ground Pin .............−7.0V to +0.5V
VTTL Pin Potential to Ground Pin ...........−0.5V to +6.0V
ECL Input Voltage (DC)............................. VEE to +0.5V
ECL Output Current
(DC Output HIGH) .........................................−50 mA
TTL Input Voltage (Note 7).................... −0.5V to +7.0V
TTL Input Current (Note 7) .............−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State
3-STATE Output................................. −0.5V to +5.5V
Current Applied to TTL
Output in LOW State (Max) twice the Rated IOL (mA)
ESD (Note 6) .....................................................2000V
100398PC Features
Differential ECL input/output structure
64 mA FAST TTL outputs
25Ω differential ECL outputs with cut-off
Bi-directional translation
2000V ESD protection
Latched outputs
3-STATE outputs
Voltage compensated operating range = −4.2V to −5.7V
64 mA FAST TTL outputs
25Ω differential ECL outputs with cut-off
Bi-directional translation
2000V ESD protection
Latched outputs
3-STATE outputs
Voltage compensated operating range = −4.2V to −5.7V
100398PC Connection Diagram
100398QI General Description
The 100398 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100398 is ideal for mixed technology applications utilizing either an ECL or TTL backplane.
The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100398 accepts TTL logic levels. A TTL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. A TTL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch transparent.
The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.
The 100398 is designed with FASTTM TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All Inputs have 50 kΩ pull-down resistors.
100398QI Maximum Ratings
Storage Temperature (TSTG)............. −65°C to +150°C
Maximum Junction Temperature
(TJ)............................................................... +150°C
VEE Pin Potential to Ground Pin .............−7.0V to +0.5V
VTTL Pin Potential to Ground Pin ...........−0.5V to +6.0V
ECL Input Voltage (DC)............................. VEE to +0.5V
ECL Output Current
(DC Output HIGH) .........................................−50 mA
TTL Input Voltage (Note 7).................... −0.5V to +7.0V
TTL Input Current (Note 7) .............−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State
3-STATE Output................................. −0.5V to +5.5V
Current Applied to TTL
Output in LOW State (Max) twice the Rated IOL (mA)
ESD (Note 6) .....................................................2000V
Maximum Junction Temperature
(TJ)............................................................... +150°C
VEE Pin Potential to Ground Pin .............−7.0V to +0.5V
VTTL Pin Potential to Ground Pin ...........−0.5V to +6.0V
ECL Input Voltage (DC)............................. VEE to +0.5V
ECL Output Current
(DC Output HIGH) .........................................−50 mA
TTL Input Voltage (Note 7).................... −0.5V to +7.0V
TTL Input Current (Note 7) .............−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State
3-STATE Output................................. −0.5V to +5.5V
Current Applied to TTL
Output in LOW State (Max) twice the Rated IOL (mA)
ESD (Note 6) .....................................................2000V
100398QI Features
Differential ECL input/output structure
64 mA FAST TTL outputs
25Ω differential ECL outputs with cut-off
Bi-directional translation
2000V ESD protection
Latched outputs
3-STATE outputs
Voltage compensated operating range = −4.2V to −5.7V
64 mA FAST TTL outputs
25Ω differential ECL outputs with cut-off
Bi-directional translation
2000V ESD protection
Latched outputs
3-STATE outputs
Voltage compensated operating range = −4.2V to −5.7V
100398QI Connection Diagram
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