ispXPGA 1200

                                                                               1.8V                                2.5V/3.3V
Supply Voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . .-0.5 to 2.5V . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage (V_CCP) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
Output Supply Voltage (V_CCO) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . .-0.5 to 4.5V
IEEE 1149.1 TAP Supply Voltage (V_CCJ) . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
Input Voltage Applied4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . 0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150. . . . . .  . . .65 to 150
Junction Temperature (T_J) with Power Applied . . -55 to 150. . . . . . .  . . -55 to 150
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications).
2. Compliance with the Lattice Thermal Management technical note is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V_IH (MAX) + 2) volts is permitted for a duration of <20ns

The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned either at the board level or the device level.

The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its associated global clock pin, and its output is routed to the associated global clock net. For example, PLL0 receives its clock input from the GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLL also has the ability to output a secondary clock that is a division of the primary clock output. When using the secondary clock, the secondary clock will be routed to the neighboring global clock net. For example, PLL0 will drive its primary clock output on the CLK0 global clock net and its secondary clock output will drive the CLK1 global clock net. Additionally, each PLL has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST signal can be generated through routing or a dedicated dual-function I/O pin. The PLL_FBK signal can be generated through a dedicated dual-function I/O pin or internally from the Global Clock net associated with the PLL. The PLL_LOCK signal feeds routing directly from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RST and PLL_FBK signals are generated.

Each PLL has four dividers associated with it, M, N, V, and K. The M divider is used to divide the clock signal, while
the N divider is used to multiply the clock signal. The V divider allows the VCO frequency to operate at higher frequencies than the clock output, thereby increasing the frequency range. The K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and feeds to the adjacent global clock
net. Different combinations of these dividers allow the user to synthesize clock frequencies. Figure 16 shows the
ispXPGA PLL block diagram.

The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the PLL. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL Usage and Design Guidelines, available at www.latticesemi.com.