Features: ` High Performance
-fMAX = 400MHz maximum operating frequency
-tPD = 2.5ns propagation delay
-Up to four global clock pins with programmable clock polarity control
-Up to 80 PTs per output
` Ease of Design
-Enhanced macrocells with individual clock, reset, preset and clock enable controls
-Up to four global OE controls
-Individual local OE control per I/O pin
-Excellent First-Time-FitTM and refit
-Fast path, SpeedLockingTM Path, and wide-PT path
-Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
` Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)
-Typical static current 10A (4032Z)
-Typical static current 1.3mA (4000C)
-1.8V core low dynamic power
` Broad Device Offering
-Multiple temperature range support
Commercial: 0 to 90°C junction (Tj)
Industrial: -40 to 105°C junction (Tj)
Automotive: -40 to 130°C junction (Tj)
` Easy System Integration
-Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
-Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies
-5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
-Hot-socketing
-Open-drain capability
-Input pull-up, pull-down or bus-keeper
-Programmable output slew rate
-3.3V PCI compatible
-IEEE 1149.1 boundary scan testable
-3.3V/2.5V/1.8V In-System Programmable (ISP™) using IEEE 1532 compliant interface
-I/O pins with fast setup pathSpecifications ispMACH 4000C/Z ispMACH 4000B ispMACH 4000V
(1.8V) (2.5V) (3.3V)
Supply Voltage (VCC) . . . . . . . . . . . . . . ............... -0.5 to 2.5V . . . . .-0.5 to 5.5V. . . . . .. -0.5 to 5.5V
Output Supply Voltage (VCCO) . . . . . . . . . . . . ..... -0.5 to 4.5V . . . . .-0.5 to 4.5V. . . . . .. -0.5 to 4.5V
Input or I/O Tristate Voltage Applied4, 5 . . . . . .. .-0.5 to 5.5V . . . . ..-0.5 to 5.5V. . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . .. . . . ........-65 to 150°C. . . -65 to 150°C . . . . .-65 to 150°C
Junction Temperature (Tj) with Power Applied . -55 to 150°C. . . .-55 to 150°C . . . . . .-55 to 150°C
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
DescriptionThe high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice's two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability,routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/ 2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment.
ispMACH 4000B Data Sheet
