Position: Home  > All Categories> Integrated Circuits (ICs) > ispMACH4000ZE

ispMACH4000ZE

Features: High Performance• f MAX = 260MHz maximum operating frequency• t PD = 4.4ns propagation delay• Up to four global clock pins with programmable clock polarity control• Up to 80 PTs per output Ease of Design• Flexible CPLD macrocells with individual clock, rese...

product image

ispMACH4000ZE Picture
See larger image
SeekIC No. : 004381231 Detail

ispMACH4000ZE: Features: High Performance• f MAX = 260MHz maximum operating frequency• t PD = 4.4ns propagation delay• Up to four global clock pins with programmable clock polarity control•...

ispMACH4000ZE Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
ispMACH4000ZE
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2025/2/15

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

High Performance
• f MAX = 260MHz maximum operating frequency
• t PD = 4.4ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output
Ease of Design
• Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit TM and refit
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
Ultra Low Power
• Standby current as low as 10A typical
• 1.8V core; low dynamic power
• Operational down to 1.6V V CC
• Superior solution for power sensitive consumer applications
• Per pin pull-up, pull-down or bus keeper control
* • Power Guard with multiple enable signals*
Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support
   Commercial: 0 to 90 junction (Tj)
   Industrial: -40 to 105 junction (Tj)
• Space-saving packages
Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
• Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
• On-chip user oscillator and timer*


Specifications

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . .. . -0.5 to 2.5V
Output Supply Voltage (VCCO) . . . . . . . . . . . . . .. . -0.5 to 4.5V
Input or I/O Tristate Voltage Applied4, 5 . . . . . .. . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150
Junction Temperature (Tj) with Power Applied . . . -55 to 150

1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6V is permitted for a duration of <20ns.
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.


Description

The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.

The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards compatible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to a V CCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Potentiometers, Variable Resistors
RV24YN
WXD4-23-3W
Inductors, Coils, Chokes
DR127-330-R
SD53-100-R
Audio Products
HUC1002
WM-64CT
Crystals and Oscillators
WT325BI0030.000000
2SB49
Memory Cards, Modules
WT32
VTL5C7
Kits
IT243
UVSC-110-4E1
View more