ispLSI 81080V

Features:

* SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
   - 3.3V Power Supply
   - 60,000 PLD Gates/1080 Macrocells
   - 192-360 I/O Pins Supporting 3.3V/2.5V I/O
   - 1440 Registers
   - High-Speed Global and Big Fast Megablock (BFM) Interconnect
   - Wide 20-Macrocell Generic Logic Block (GLB) for High Performance
   - Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc.
   - PCB-Efficient Ball Grid Array (BGA) Package Options
* HIGH-PERFORMANCE E² CMOS^(R)TECHNOLOGY
   - fmax = 125 MHz Maximum Operating Frequency
   - tpd = 8.5 ns Propagation Delay
   - Electrically Erasable and Reprogrammable
   - Non-Volatile
   - Programmable Speed/Power Logic Path Optimization
* IN-SYSTEM PROGRAMMABLE
   - Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
   - Reprogram Soldered Devices for Faster Debugging
* 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
* ARCHITECTURE FEATURES
   - Enhanced Pin-Locking Architecture, Symmetrical Generic Logic Blocks Connected by Hierarchical Big Fast Megablock and Global Routing Planes
   - Product Term Sharing Array Supports up to 28 Product Terms per Macrocell Output
   - Macrocells Support Concurrent Combinatorial and Registered Functions
   - Embedded Tristate Bus Can Be Used as an Internal Tristate Bus or as an Extension of an External Tristate Bus
   - Macrocell and I/O Registers Feature Multiple Control Options, Including Set, Reset and Clock Enable
   - I/O Pins Support Programmable Bus Hold, Pull-Up,Open-Drain and Slew Rate Options
   - Separate VCCIO Power Supply to Support 3.3V or2.5V Input/Output Logic Levels
   - I/O Cell Register Programmable as Input Register for Fast Setup Time or Output Register for Fast Clock to Output Time 
* ispDesignEXPERT^(TM) LOGIC COMPILER AND COM-PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   - Superior Quality of Results
   - Tightly Integrated with Leading CAE Vendor Tools
   - Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER(TM)
   - PC and UNIX Platforms


Specifications

Supply Voltage V_cc .................................. .-0.5 to +5.4V
Input Voltage Applied............................... .-0.5 to +5.6V
Tri-Stated Output Voltage Applied........... .-0.5 to +5.6V
Storage Temperature..................................-65 to 150
Case Temp. with Power Applied .................-55 to 125
Max. Junction Temp. (T_J) with Power Applied ...  ...150
1. Stresses above  those listed  under  the "Absolute  Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.


Description

The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macro- cells and a Global Routing Plane (GRP) structureinterconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 120 registered macrocells arranged in six groups of 20, a group of 20 being referred to as a Generic Logic Block, or GLB. Within the Big Fast Megablock, a Big Fast Megablock Routing Pool (BRP) interconnects the six GLBs to each other and to 24 Big Fast Megablock I/O cells with optional I/O registers. The Global Routing Plane which interconnects the Big Fast Megablocks has additional global I/Os with optional I/O registers. The 192-I/O version contains 72 Big Fast Megablock I/Os and 120 global I/Os, while the 360-I/O version contains 216 Big Fast Megablock I/Os and 144 global I/Os.