ispLSI883

Features: • HIGH-DENSITY PROGRAMMABLE LOGIC - High-Speed Global Interconnect - 2000 PLD Gates - 32 I/O Pins, Four Dedicated Inputs - 96 Registers - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. - Small Logic Block Size for Random Logic - Security Cell Prevents U...

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SeekIC No. : 004381223 Detail

ispLSI883: Features: • HIGH-DENSITY PROGRAMMABLE LOGIC - High-Speed Global Interconnect - 2000 PLD Gates - 32 I/O Pins, Four Dedicated Inputs - 96 Registers - Wide Input Gating for Fast Counters, State M...

floor Price/Ceiling Price

Part Number:
ispLSI883
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• HIGH-DENSITY PROGRAMMABLE LOGIC
   - High-Speed Global Interconnect
   - 2000 PLD Gates
   - 32 I/O Pins, Four Dedicated Inputs
   - 96 Registers
   - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
   - Small Logic Block Size for Random Logic
   - Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   - fmax = 60 MHz Maximum Operating Frequency
   - tpd = 20 ns Propagation Delay
   - TTL Compatible Inputs and Outputs
   - Electrically Erasable and Reprogrammable
   - Non-Volatile E2CMOS Technology
   - 100% Tested
• IN-SYSTEM PROGRAMMABLE
   - In-System Programmable™ (ISP™) 5-Volt Only
   - Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality
   - Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM 
   SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
   OF FIELD PROGRAMMABLE GATE ARRAYS
   - Complete Programmable Device Can Combine Glue Logic and Structured Designs
   - Three Dedicated Clock Input Pins
   - Synchronous and Asynchronous Clocks
   - Flexible Pin Placement
   - Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ LOGIC COMPILER AND COMPLETE
   ISP DEVICE DESIGN SYSTEMS FROM HDL
   SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   - Superior Quality of Results
   - Tightly Integrated with Leading CAE Vendor Tools
   - Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
   - PC and UNIX Platforms



Pinout

  Connection Diagram


Specifications

Supply Voltage Vcc ....................................-0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature .............................. -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ..... 150°C

1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).




Description

The ispLSI 1016/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD- 883. This military grade device contains 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016/883 features 5- Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 1016/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016/883 device. Each GLB has 18 inputs, a  rogrammable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.




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