ispLSI2032

Features:

* ENHANCEMENTS
   - ispLSI 2032A is Fully Form and Function Compatible to the ispLSI 2032, with Identical Timing
       Specifcations and Packaging
   - ispLSI 2032A is Built on an Advanced 0.35 Micron E²CMOS^R  Technology
* HIGH DENSITY PROGRAMMABLE LOGIC
   - 1000 PLD Gates
   - 32 I/O Pins, Two Dedicated Inputs
   - 32 Registers
   - High Speed Global Interconnect
   - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
   - Small Logic Block Size for Random Logic
* HIGH PERFORMANCE E²CMOS^R  TECHNOLOGY
   - fmax = 180 MHz Maximum Operating Frequency
   - tpd = 5.0 ns Propagation Delay
   - TTL Compatible Inputs and Outputs
   - Electrically Erasable and Reprogrammable
   - Non-Volatile
   - 100% Tested at Time of Manufacture
   - Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
   - In-System Programmable (ISP^TM) 5V Only
   - Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
   - Reprogram Soldered Devices for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD    PROGRAMMABLE GATE ARRAYS
   - Complete Programmable Device Can Combine Glue Logic and Structured Designs
   - Enhanced Pin Locking Capability
   - Three Dedicated Clock Input Pins
   - Synchronous and Asynchronous Clocks
   - Programmable Output Slew Rate Control to Minimize Switching Noise
   - Flexible Pin Placement
   - Optimized Global Routing Pool Provides Global Interconnectivity

Pinout




Specifications

Supply Voltage V_cc ....................................-0.5 to +7.0V
Input Voltage Applied.........................-2.5 to VCC +1.0V
Off-State Output Voltage Applied ......-2.5 to VCC +1.0V
Storage Temperature..................................-65 to 150C
Case Temp. with Power Applied .................-55 to 125C
Max. Junction Temp. (T_J) with Power Applied ....... 150C
1. Stresses above  those listed  under  the "Absolute  Maximum Ratings" may cause permanent damage to the device. Functional operation of the  device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).


Description

The ispLSI 2032 and 2032A are High Density Program-mable Logic Devices. The devices contain 32 Registers,32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing  Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7(Figure 1). There are a total of eight GLBs in the ispLSI2032 and 2032A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any FOR NEW DESIGNS GLB on the device.