ispLSI1024EA

The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024EA features 5V in-system  diagnostic capabilities via IEEE 1149.1 Test Access Port. The ispLSI 1024EA device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. A functional superset of the ispLSI 1024 architecture, the ispLSI 1024EA device adds user selectable 3.3V or 5V I/O and open-drain output options.

The basic unit of logic on the ispLSI 1024EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1.D7 (Figure 1). There are a total of 24 GLBs in the ispLSI 1024EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.