ispLSI1024

Features:

* HIGH-DENSITY PROGRAMMABLE LOGIC
  - High-Speed Global Interconnect
  - 4000 PLD Gates
  - 48 I/O Pins, Six Dedicated Inputs
  - 144 Registers
  - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
  - Small Logic Block Size for Fast Random Logic
  - Security Cell Prevents Unauthorized Copying
* HIGH PERFORMANCE E²CMOS^(R)TECHNOLOGY
  - fmax = 60 MHz Maximum Operating Frequency
  - tpd = 20 ns Propagation Delay
  - TTL Compatible Inputs and Outputs
  - Electrically Erasable and Reprogrammable
  - Non-Volatile E² CMOS Technology
  - 100% Tested
* IN-SYSTEM PROGRAMMABLE
   - In-System Programmable(TM) (ISP(TM)) 5-Volt Only
   - Increased Manufacturing Yields, Reduced Time-to-Market, and Improved Product Quality
   - Reprogram Soldered Devices for Faster Debugging
* COMBINES EASE OF USE AND THE  FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX-IBILITY OF    FIELD PROGRAMMABLE GATE ARRAYS
   - Complete Programmable Device Can Combine Glue Logic and Structured Designs
   - Four Dedicated Clock Input Pins
   - Synchronous and Asynchronous Clocks
   - Flexible Pin Placement
   - Optimized Global Routing Pool Provides Global Interconnectivity
* ispDesignEXPERT^(TM) LOGIC COMPILER AND COM-PLETE IS DEVICEDESIGNSYSTEMSFROMHDLSYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   - Superior Quality of Results
   - Tightly Integrated with Leading CAE Vendor Tools
   - Productivity Enhancing Timing Analyzer, ExploreTools, Timing Simulator and ispANALYZER^(TM)
   - PC and UNIX Platforms unctional Block Diagram

Pinout




Specifications

Supply Voltage V_cc ...................................-0.5 to +7.0V
Input Voltage Applied........................-2.5 to V_CC +1.0V
Off-State Output Voltage Applied .....-2.5 to V_CC +1.0V
Storage Temperature................................-65 to 150
Case Temp. with Power Applied ..............-55 to 125
Max. Junction Temp. (T_J) with Power Applied ... 150
1. Stresses above  those listed  under  the "Absolute  Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).

Description

The ispLSI 1024/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883.  This military grade device contains 144 Registers,48 Universal I/O pins, six Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing  Pool(GRP).  The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024/883 features 5-Volt in-system programmability and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1024/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0,A1 .. C7 (see figure 1).  There are a total of 24 GLBs in the ispLSI 1024/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs.  All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.