ispGDX 80VA Selling Leads, Price trend, ispGDX 80VA DataSheet download, circuit diagram from SeekIC.com

Features: * IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY - Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement - Any Input to Any Output Routing - Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation - Spac...

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SeekIC No. : 004381183 Detail

ispGDX 80VA: Features: * IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY - Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement - Any I...

ispGDX 80VA Data Sheet

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Part Number:: ispGDX 80VA
Supply Ability:: 5000

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15 Days

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Upload time: 2024/12/21

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Product Details

Description

Features:

* IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY
   - Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement
   - "Any Input to Any Output" Routing
   - Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation
   - Space-Saving PQFP and BGA Packaging
   - Dedicated IEEE 1149.1-Compliant Boundary Scan Test
* HIGH PERFORMANCE E² CMOS^(R)TECHNOLOGY
   - 3.3V Core Power Supply
   - 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay
   - 250MHz Maximum Clock Frequency
   - TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)
   - Low-Power: 16.5mA Quiescent Icc
   - 24mA IOL Drive with Programmable Slew Rate Control Option
   - PCI Compatible Drive Capability
   - Schmitt Trigger Inputs for Noise Immunity
   - Electrically Erasable and Reprogrammable
   - Non-Volatile E² CMOS Technology
* ispGDXV(TM) OFFERS THE FOLLOWING ADVANTAGES
   - 3.3V In-System Programmable Using Boundary Scan est Access Port (TAP)
   - Change Interconnects in Seconds
* FLEXIBLE ARCHITECTURE
   - Combinatorial/Latched/Registered Inputs or Outputs
   - Individual I/O Tri-state Control with Polarity Control
   - Dedicated Clock/Clock Enable Input Pins (two) or Programmable Clocks/Clock Enables from I/O Pins (20)
   - Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
   - Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX
   - Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins
   - Outputs Tri-state During Power-up ("Live Insertion"Friendly)
* DESIGN SUPPORT THROUGH LATTICE'S ispGDX DEVELOPMENT SOFTWARE
   - MS Windows or NT / PC-Based or Sun O/S
   - Easy Text-Based Design Entry
   - Automatic Signal Routing
   - Program up to 100 ISP Devices Concurrently
   - Simulator Netlist Generation for Easy Board-Level Simulation

Specifications

Supply Voltage V_cc ................................. . -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature..................................-65 to 150
Case Temp. with Power Applied ................-55 to 125
Max. Junction Temp. (T_J) with Power Applied ... ...150
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.

Description

The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface require-ments including:
* Multi-Port Multiprocessor Interfaces
* Wide Data and Address Bus Multiplexing(e.g. 16:1 High-Speed Bus MUX)
* Programmable Control Signal Routing(e.g. Interrupts, DMAREQs, etc.)
* Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces

The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.

The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout-ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs

ispGDX 80VA

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