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ispGDX2

Features: High Performance Bus Switching• High bandwidth Up to 12.8 Gbps (SERDES) Up to 38 Gbps (without SERDES)• Up to 16 (15x10) FIFOs for data buffering• High speed performance fMAX= 360MHz tPD= 3.0ns tCO= 2.9ns tS= 2.0ns• Built-in programmable control logic capability&...

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SeekIC No. : 004381184 Detail

ispGDX2: Features: High Performance Bus Switching• High bandwidth Up to 12.8 Gbps (SERDES) Up to 38 Gbps (without SERDES)• Up to 16 (15x10) FIFOs for data buffering• High speed performance...

ispGDX2 Data Sheet

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Part Number:
ispGDX2
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/9/16

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Product Details

Description



Features:

High Performance Bus Switching
• High bandwidth
Up to 12.8 Gbps (SERDES)
Up to 38 Gbps (without SERDES)
• Up to 16 (15x10) FIFOs for data buffering
• High speed performance
fMAX= 360MHz
tPD= 3.0ns
tCO= 2.9ns
tS= 2.0ns
• Built-in programmable control logic capability
• I/O intensive: 64 to 256 I/Os
• Expanded MUX capability up to 188:1 MUX
sysCLOCK™ PLL
• Frequency synthesis and skew management
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
• Up to four PLLs
sysIO™ Interfacing
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for standard board interfaces
• SSTL 2/3 Class I and II support
• HSTL Class I, III and IV support
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Two Options Available
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI ("E-Series")
sysHSI Blocks Provide up to 16 High-speed Channels
• Serializer/de-serializer (SERDES) included
• Clock Data Recovery (CDR) built in
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
Encoding / decoding
Bit alignment
Symbol alignment
• 8B/10B support
Bit alignment
Symbol alignment
• Source Synchronous support
Flexible Programming and Testing
• IEEE 1532 compliant In-System Programmability (ISP™)
• Boundary scan test through IEEE 1149.1 interface
• 3.3V, 2.5V or 1.8V power supplies
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces


Specifications

                                                                          ispGDX2C (1.8V)                      ispGDX2B/V (2.5/3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .. . . . . -0.5 to 5.5V
PLL Supply Voltage VCCP. . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Supply Voltage VCCO . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . .. . . -0.5 to 4.5V
JTAG Supply Voltage (VCCJ) . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input or I/O Tristate Voltage Applied 4, 5 . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 . . . . . . . .  . . . . . -65 to 150
Junction Temp. (TJ) with Power Applied . . . . . . . . -55 to 150 . . . . . . . . . . . . . . . -55 to 150

1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications).
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIH (MAX)+2) volts is permitted for a duration of <20ns.
5. A maximum of 64 I/Os per device with VIN > 3.6V is allowed.




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