Features: • Zoom (from VGA) and shrink (from UXGA) scaling• Integrated 8-bit triple-channel ADC / PLL• Integrated Ultra-Reliable DVI 1.0-compliant receiver• High-Bandwidth Digital Content Protection (HDCP)• On-chip programmable OnPanel timing controller• Embedde...
gm5115-H: Features: • Zoom (from VGA) and shrink (from UXGA) scaling• Integrated 8-bit triple-channel ADC / PLL• Integrated Ultra-Reliable DVI 1.0-compliant receiver• High-Bandwidth Di...
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PARAMETER | SYMBOL | MIN | TYP | MAX | UNITS |
3.3V Supply Voltages (1,2) | VVDD_3.3 | -0.3 | 3.6 | V | |
2.5V Supply Voltages (1.2) | VVDD_2.5 | -0.3 | 2.75 | V | |
Input Voltage (5V tolerant inputs) (1,2) | VIN5Vtol | -0.3 | 5.5 | V | |
Input Voltage (non 5V tolerant inputs) (1,2) | VIN | -0.3 | 3.6 | V | |
Electrostatic Discharge | VESD | ±2.0 | kV | ||
Latch-up | ILA | ±100 | mA | ||
Ambient Operating Temperature | TA | 0 | 70 | ||
Storage Temperature | TSTG | -40 | 125 | ||
Operating Junction Temp. | TJ | 0 | 125 | ||
Thermal Resistance (Junction to Air) Natural Convection (3) gm5115 gm5125 |
JA_5115 JA_5125 |
32.4 22.0 |
/W | ||
Thermal Resistance (Junction to Case) Convection (4) gm5115 gm5125 |
JC_5115 JC_5125 |
13.9 10.1 |
/W | ||
Soldering Temperature (30 sec.) | TSOL | 220 | |||
Vapor Phase Soldering (30 sec.) | TVAP | 220 |
A functional block diagram of gm5115/25 is illustrated below. Each of the functional units shown is described in the following sections.
The gm5115/25 features three clock inputs. All additional clocks are internal clocks derived from one or more of these:
1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. A 14.3 MHz TV crystal is recommended. Other crystal frequencies may be used, but require custom programming. This is illustrated in Figure 4 below.
Alternatively, a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin (leave XTAL as N/C in this case). This is illustrated in Figure 7 below. This option is selected by connecting a 10K pull-up to ROM_ADDR13 (refer to Table 18). See also Table 14.
2. DVI Differential Input Clock (RC+ and RC-)
3. Host Interface Transfer Clock (HCLK)