dsPIC30F6015

DSP Engine Features:
• Dual data fetch
• Accumulator write back for DSP operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier
• All DSP instructions single cycle
• ±16-bit single-cycle shift

Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
- Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• 3-wire SPITM modules (supports 4 Frame modes)
• I²CTM module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
• 2 UART modules with FIFO Buffers
• 2 CAN modules, 2.0B compliant (dsPIC306010A)
• 1 CAN module, 2.0B compliant (dsPIC306015)

Motor Control PWM Module Features:
• 8 PWM output channels
- Complementary or Independent Output modes
- Edge and Center-Aligned modes
• 4 duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead-Time control for Complementary mode
• Manual output control
• Trigger for A/D conversions

Quadrature Encoder Interface Module Features:
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow

Absolute Maximum Ratings(†)
Ambient temperature under bias....................................................................-40°C to +125°C
Storage temperature .................................................................................... -65°C to +150°C
Voltage on any pin with respect to V_SS (except V_DD and MCLR) (Note 1)...-0.3V to (V_DD + 0.3V)
Voltage on V_DD with respect to V_SS ..................................................................... -0.3V to +5.5V
Voltage onMCLR with respect to V_SS.................................................................... 0V to +13.25V
Maximum current out of V_SS pin ........................................................................................300 mA
Maximum current into VDD pin (Note 2)..............................................................................250 mA
Input clamp current, I_IK (V_I < 0 or V_I > V_DD) ....................................................................±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DD) ..............................................................±20 mA
Maximum output current sunk by any I/O pin.........................................................................25 mA
Maximum output current sourced by any I/O pin ...................................................................25 mA
Maximum current sunk by all ports .......................................................................................200 mA
Maximum current sourced by all ports (Note 2).....................................................................200 mA

Note 1: Voltage spikes below V_SS at the MCLR/V_PP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/V_PP pin, rather than pulling this pin directly to V_SS.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 24-6.

†NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.