dsPIC30F5011

DSP Features:
• Dual data fetch
• Modulo and Bit-reversed modes
• Two 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single cycle hardware fractional/ integer multiplier
• All DSP instructins are single cycle
- Multiply-Accumulate (MAC) operation
• Single cycle ±16 shift

Peripheral Features:
• High current sink/source I/O pins: 25 mA/25 mA
• Five 16-bit timers/counters; optionally pair up 16- bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions:
• Data Converter Interface (DCI) supports common audio Codec protocols, including I2S and AC'97
• 3-wire SPI™ modules (supports 4 Frame modes)
• I²C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
• Two addressable UART modules with FIFO buffers
• Two CAN bus modules compliant with CAN 2.0B standard

Analog Features:
• 12-bit Analog-to-Digital Converter (A/D) with:
- 100 Ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low Voltage Detection (PLVD)
• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation

Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................-40°C to +125°C
Storage temperature ................................................................................... -65°C to +150°C
Voltage on any pin with respect to V_SS (except V_DD and MCLR) (Note 1)...-0.3V to (V_DD + 0.3V)
Voltage on VDD with respect to V_SS .................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to V_SS .................................................................. 0V to +13.25V
Maximum current out of V_SS pin .......................................................................................300 mA
Maximum current into V_DD pin (Note 2).............................................................................250 mA
Input clamp current, I_IK (V_I < 0 or V_I > V_DD) ...................................................................±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DD) ..............................................................±20 mA
Maximum output current sunk by any I/O pin.......................................................................25 mA
Maximum output current sourced by any I/O pin .................................................................25 mA
Maximum current sunk by all ports .....................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................200 mA
Note 1: Voltage spikes below V_SS at the MCLR/V_PP pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/V_PP pin, rather than pulling this pin directly to V_SS.
2: Maximum allowable current is a function of device maximum power dissipaton. See Table 23-2 for PDMAX.

†NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table.